92 lines
4 KiB
Markdown
92 lines
4 KiB
Markdown
---
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tags: [logic-gates, binary, memory]
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---
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# Latches
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The **combinatorial digital circuits** we have looked at so far have been
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non-sequential. The outcome is a function of its immediate set of inputs and
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everything happens at once: there is no means of storing state for future use.
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In other words there is no _[memory](Memory.md)_.
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In contrast, the output of a **sequential digital circuit** depends not only on
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its present set of inputs but also on past inputs to the circuit. It has some
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knowledge of its own previous state through the existence of memory. This can be
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implemented via components that allow for the **storage and retrieval of binary
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data**.
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## What is a latch?
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A latch is a circuit component that wor
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The **SR Latch** (for "set/reset") has two inputs: _S_ (for "set") and _R_ (for
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"reset") and one output, _Q_. _Q_ stands for the bit that is remembered. (There
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is also _not-Q_ which is the opposite of whatever _Q_ is currently set to.)
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The SR Latch goes through the following state changes:
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- When _S_ is set to 1, output _Q_ becomes 1 also
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- When _S_ goes to 0, _Q_ remains 1
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- When _R_ is set to 1, the memory bit is cleared and _Q_ becomes 0.
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- _Q_ remains at 0 even if _R_ goes back to 0
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This is represented more clearly in the table below:
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| S | R | Q | Operation |
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| --- | --- | --- | ------------- |
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| 1 | 1 | X | Invalid, null |
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The most succinct account of a latch:
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> A latch is a 1-bit memory device that has a state _Q_ of either 1 or 0. The
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> _S_ input sets _Q_ to 1 and the _R_ input resets _Q_ to 0.
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_The representation of an SR Latch in a digital circuit diagram_:
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## Creating a latch circuit
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The circuit diagram latch symbol obviously encapsulates more complex
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functionality that occurs at the sub-circuit level. We will demonstrate how this
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functionality can be achieved with two
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[NOR](Logic_gates.md#nor-gate) gates.
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The two gates are in a **cross-coupled configuration**. This basically means
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that the wires are crossed back on themselves such that the output of one is
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also an input of the other at a single stage in the sequence.
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The circuit is created as follows:
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Interactive version:
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<iframe src="https://circuitverse.org/simulator/embed/nor-latch-0869192c-7d7b-4161-b13f-3f72c1bce8e9" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="400" width="600" allowFullScreen></iframe>
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<br />
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Let's talk through the logic at each state change:
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- When _S_ is set to 1, output _Q_ becomes 1 also
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- N1 is receiving 1 from S and 0 from R by way of N2. This is the inversion of
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OR so TF equals F. Thus N1 is outputting 0.
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- Thus N2 is receiving 0 from N1 as its top input and 0 from R as its bottom
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input. It is therefore outputting 1 because with NOR, FF equals T. For this
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reason, _Q_ is 1 because is directly connected to _R_.
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- When _S_ goes to 0, _Q_ remains 1
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- N2 is receiving 0 from N1 as the top input and 0 from R as the bottom input
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hence the overall input is FF which means N2 is outputting T and Q remains 1
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- N1 is outputting 0 because it is receiving 0 as its top input and 1 from its
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bottom input
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- When _R_ is set to 1, the memory bit is cleared and _Q_ becomes 0.
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- N2 is receiving 1 from R as its bottom input and 1 from the output of N1 as
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its top input. Therefore it is outputting TT which in NOR evaluates to F
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hence Q is 0
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- N1 is outputting 1 because it is receiving 0 from S as its top input and 0
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from its bottom input coming from N2. FF equals T in NOR therefore 1 is
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outputting 1
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- _Q_ remains at 0 even if _R_ goes back to 0
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- N2 is receiving 0 as its bottom input from R and 1 as its top input from N1.
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TF equals F in NOR hence the output of N2 is 0 and Q remains 0
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- N1 is outputting 1 because it is receiving 0 as its top input from S and 0
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as its bottom input from N2. FF equals T in NOR hence N1 is 1
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