76 lines
5 KiB
Markdown
76 lines
5 KiB
Markdown
---
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categories:
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- Computer Architecture
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- Electronics
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- Hardware
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tags: [logic-gates, binary, memory]
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---
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# Latches
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The combinatorial digital circuits we have looked at so far have been non-sequential. The outcome is a function of its immediate set of inputs and everything happens at once: there is no means of storing state for future use. In other words there is no _[memory](/Hardware/Memory/Memory.md)_.
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In contrast, a sequential digital circuit's output depends not only on its present set of inputs but also on past inputs to the circuit. It has some knowledge of its own previous state through the existence of memory. This can be implemented via components that allow for the **storage and retrieval of binary data**.
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## What is a latch?
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A latch is a circuit component that works as a very basic memory device. It is capable of setting and resetting a single bit. We can remember what it does by thinking of a door latch: once you turn the key the lock is set, when you turn it back it is unset.
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The **SR Latch** (for "set/reset") has two inputs: _S_ (for "set") and _R_ (for "reset") and one output, _Q_. _Q_ stands for the bit that is remembered. (There is also _not-Q_ which is the opposite of whatever _Q_ is currently set to.)
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The SR Latch goes through the following state changes:
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- When _S_ is set to 1, output _Q_ becomes 1 also
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- When _S_ goes to 0, _Q_ remains 1
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- When _R_ is set to 1, the memory bit is cleared and _Q_ becomes 0.
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- _Q_ remains at 0 even if _R_ goes back to 0
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This is represented more clearly in the table below:
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| S | R | Q | Operation |
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| --- | --- | ----------------------- | ------------- |
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| 0 | 0 | Maintain previous value | Hold |
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| 0 | 1 | 0 | Reset |
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| 1 | 0 | 1 | Set |
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| 1 | 1 | X | Invalid, null |
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Important to note that this works if we set 1 or 0 as the bit to be remembered, not just if S is set to 1. Either way, the remembered bit will be represented by _Q_ regardless of how many times we toggle _S_ after the initial setting.
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_The representation of an SR Latch in a digital circuit diagram_:
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## Creating a latch circuit
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There is more than one way of implementing a latch with logic gates. We will look at two formulations which both use a single type of gate: [NANDs](/Hardware/Logic_Gates/Logic_gates.md#nand-gate) and [NORs](/Hardware/Logic_Gates/Logic_gates.md#nor-gate) (both universal logic gates).
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In each case, the gates are in a **cross-coupled configuration**. This basically means that the wires are crossed back on themselves such that the output of one is also an input of the other at a single stage in the sequence.
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### NOR latch
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<iframe src="https://circuitverse.org/simulator/embed/nor-latch-0869192c-7d7b-4161-b13f-3f72c1bce8e9" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="400" width="600" allowFullScreen></iframe>
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<br />
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Let's talk through the logic at each state change:
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- When _S_ is set to 1, output _Q_ becomes 1 also
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- N1 is receiving 1 from S and 0 from R by way of N2. This is the inversion of OR so TF equals F.
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- Hence N2 (which is the state of Q) is receiving 0 from N1 as its top input and 0 from R as its bottom input. In NOR, FF equals T hence Q is 1
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- When _S_ goes to 0, _Q_ remains 1
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- N2 is receiving 0 from N1 as the top input and 0 from R as the bottom input hence the ohverall input is FF which means NT is outputting T and Q remains 1
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- N1 is outputting 0 because it is receiving 0 as its top input and 1 from its bottom input
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- When _R_ is set to 1, the memory bit is cleared and _Q_ becomes 0.
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- N2 is receiving 1 from R as its bottom input and 1 from the output of N1 as its top input. Therefore it is outputting TT which in NOR evaluates to F hence Q is 0
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- N1 is outputting 1 because it is receiving 0 from S as its top input and 0 from its bottom input coming from N2. FF equals T in NOR therefore 1 is outputting 1
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- _Q_ remains at 0 even if _R_ goes back to 0
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- N2 is receiving 0 as its bottom input from R and 1 as its top input from N1. TF equals F in NOR hence the output of N2 is 0 and Q remains 0
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- N1 is outputting 1 because it is receiving 0 as its top input from S and 0 as its bottom input from N2. FF equals T in NOR hence N1 is 1
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### NAND latch
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With a NAND-based memory implementation we have two inputs: _I_ which is the bit we want to store in memory and _S_ which sets it. There is a single output _O_ which
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<iframe src="https://circuitverse.org/simulator/embed/nand-mem?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="500" width="600" allowFullScreen></iframe>
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