214 lines
8.7 KiB
Markdown
214 lines
8.7 KiB
Markdown
---
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tags: [memory, motherboard]
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---
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# Memory
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## Why do we need memory?
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> A CPU is just an operator on memory. It reads its instructions and data from
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> the memory and writes back out to the memory. (Ward 2021)
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When a [CPU](CPU_architecture.md) executes a program,
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it needs a place to store the program's **instructions** and **related data**.
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This is the role of memory.
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## What is memory?
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The data that comprises a program is a series of bits. The basic unit of memory
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storage is a **memory cell**: a circuit that can store a single bit.
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## Memory types
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There are two types of memory: SRAM and DRAM. Both types of RAM memory are
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_volatile_ : the memory is only retained whilst the computer has a power supply
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and is wiped when the computer is rebooted. This contrasts with the memory of
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the harddisk which is non-volatile and is retained after a reboot.
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Programs that are executing are loaded into memory because the chips that
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comprise memory can read and store data much faster than the harddisk. It would
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be possible to run a program from the harddisk but it would be 500 - 1000 times
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slower than memory.
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#### DRAM
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DRAM uses capacitors to create the memory cell:
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> a **capacitor** is an electronic component that stores electrical energy in an
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> electrical field. A device which can accumulate and release electrical charge.
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In a DRAM cell, each bit of data is stored as a charge in a capacitor. The
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presence of charge represents a '1' bit and the absence of charge represents a
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'0' bit. Each of these cells is paired with a
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[transistor](Transistors.md) that
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controls the reading and writing of data.
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However capacitors lose
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[charge](Current.md) over time due
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to leaks. As a result DRAM is memory that needs to be refreshed (recharged)
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frequently. For this reason and because it only uses one transistor and
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capacitor per bit, DRAM is the less expensive form of volatile memory.
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#### SRAM
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SRAM (Static Random Access Memory) is also volatile memory but its electronical
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implementation is different. Unlike DRAM it doesn't use capacitors. Consequently
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the transistors do not leak or need to be refreshed, hence why SRAM is _static_
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and DRAM is _dynamic_.
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SRAM uses [flip flops](Flip_flops.md)
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to store the bits. It also uses multiple transistors per bit. This makes it
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faster than DRAM but more expensive. DRAM is at least ten times slower than
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SRAM.
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## The role of memory in computation
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The following steps outline the way in which memory interacts with the processor
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during computational cycles, once the
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[bootstrapping](Boot_process.md) process has completed and
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the OS kernel is itself loaded into memory.
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1. A file is loaded from the harddisk into memory.
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2. The instruction at the first address is sent to the CPU, travelling accross
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the data bus part of the [system bus](Bus.md).
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3. The CPU processes this instruction and then sends a request accross the
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address bus part of the system bus for the next instruction to the memory
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controller within the
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[chipset](Chipset_and_controllers.md).
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4. The chipset finds where this instruction is stored within the
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[DRAM](Memory.md#dram) and issues a request to
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have it read out and send to the CPU over the data bus.
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> This is a simplified account; it is not the case that only single requests are
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> passed back and forth. This would be inefficient and time-wasting. The kernel
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> sends to the CPU not just the first instruction in the requested file but also
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> a number of instructions that immediately follow it.
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Every part of the above process - the journey accross the bus, the lookup in the
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controller, the operations on the DRAM, the journey back accross the bus - takes
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multiple CPU clock cycles.
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## CPU register and cache memory
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As partly indicated in the diagram above, the CPU has its own memory in the form
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of registers and cache memory.
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Registers are a form of memory that are positioned on the same chip as the CPU.
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They are very fast but can only store a small amount of data. They are used to
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store the results of calculations and the addresses of the next instructions to
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be processed.
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The cache is SRAM memory that is separate from the DRAM memory which comprises
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the main memory. It exists in order to boost perfomance when executing the
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read/request cycles of the steps detailed above.
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There are two types of cache memory:
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- L1 cache
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- Situated on the CPU chip itself
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- Fastest to access but stores less
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- L2 cache
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- Situated outside of the CPU on its own chip
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- Slower to access than L1 but can store more data
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The L1 cache is the fastest since the data has less distance to travel when
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moving to and from the CPU. This said, the L2 cache is still very fast when
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compared to the main memory, both because it is SRAM rather than DRAM and
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because it is closer to the processor than the main memory.
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Cache controllers use complex algorithms to determine what should go into the
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cache to facilitate the best performance, but generally they work on the
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principle that what has been previously used by the CPU will be requested again
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soon. If the CPU has just asked for an instruction at memory location 555 it's
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very likely that it will next ask for the one at 556, and after that the one at
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557 and so on. The cache's controller circuits therefore go ahead and fetch
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these from slow DRAM to fast SRAM.
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## The memory hierarchy
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The diagram below compares the different forms of memory within a computing
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device in terms of speed, monetary cost and capacity:
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## Memory addresses
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> Computers assign numeric addresses to bytes of memory and the CPU can read or
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> write to those addresses
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We can think of the internals of RAM as grids of memory cells.
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Each single-bit cell in the grid can be identified using two dimensional
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coordinates, like in a graph. The coordinates are the location of that cell in
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the grid.
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Handling one bit at a time isn't very efficient so RAM accesses **multiple
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grids** of 1-bit memory cells in parallel. This allows for reads or writes of
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multiple bits at once, such as a whole byte.
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The location of a set of bits in memory is known as a **memory address**.
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### Demonstration
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Let's imagine we have a computer system that can address up to 64KB of memory
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and our system is byte addressable. This means there are
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$64 \cdot 1024 = 65,536$ bytes of memory because 1KB = 1024 bytes.
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We therefore have 65,536 addresses and each address can store one byte. So our
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addresses go from 0 to 65, 535.
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We now need to consider how many bits we need to uniquely represent an address
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on this system.
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What does this mean? Although there are approximately 64 thousand bytes of
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memory, to refer to each byte we can't just use 1, 2, 3... because computers use
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binary numbers. We need a binary number to refer to a given byte in the the 64KB
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of memory. The question we are asking is: how long does this binary number need
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to be to be able to represent each of the 64 thousand bytes?
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1 bit can represent two addresses: 0 and 1. 2 bits can represent four addresses:
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00, 01, 10, 11. The formula is as follows: number of addresses = $2^n$ where $n$
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is the number of bits.
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We need to reverse this formula to find out how many bits we need to represent a
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given number of addresses. We can do this with a
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[logarithm](Logarithms.md).
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We can reverse the formula as follows: number of bits = $\log_2$(number of
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addresses).
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In our case we have 65,536 addresses so we need $\log_2(65,536)$ bits to
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represent each address. This is approximately 16 bits. Thus a 16 bit memory
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address is needed to address 65, 546 bytes.
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Using memory addresses we end up with tables like the following:
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| Memory address | Data |
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| ---------------- | ---------------- |
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| 0000000000000000 | 1010101010101010 |
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| 0000000000000001 | 0010001001001011 |
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| 0000000000000010 | 0010001001001010 |
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This is hard to parse so we can instead use
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[hexadecimal numbers](Hexadecimal_number_system.md)
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to represent the addresses:
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| Memory address (as hex) | Data (as binary) |
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| ----------------------- | ---------------- |
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| 0x0000 | 1010101010101010 |
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| 0x0001 | 0010001001001011 |
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| 0x0002 | 0010001001001010 |
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By itself, the the data is meaningless but we know from
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[binary encoding](Binary_encoding.md) that the
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binary data will correspond to some meaningful data, such as a character or a
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colour, depending on the encoding scheme used. The above table could correspond
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to the characters for 'A', 'B' and 'C' in the ASCII encoding scheme:
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| Memory address (as hex) | Data (as binary) | Data (as ASCII) |
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| ----------------------- | ---------------- | --------------- |
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| 0x0000 | 1010101010101010 | A |
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| 0x0001 | 0010001001001011 | B |
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| 0x0002 | 0010001001001010 | C |
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