116 lines
3.6 KiB
Markdown
116 lines
3.6 KiB
Markdown
---
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tags: [nand-to-tetris]
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---
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# Hardware Description Language
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An HDL is a declarative programming language used to describe the behaviour or
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structure of
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[digital circuits](Integrated_circuits.md).
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They are used to simulate the circuit and check its response.
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The hardware designer specifies a chip's logic by writing an HDL program which
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is then rigorously tested. At this stage, a
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[hardware simulator](Hardware_simulation.md) takes the
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HDL program as input and creates a software representation of the chip logic.
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The designer can instruct the simulator to test the virtual chip on various sets
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of inputs. This is done to check the chip's functionality but also to benchmark
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a variety of other parameters such as speed of computation and energy
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consumption.
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There are many HDLs but the most popular are VHDL ("very high speed
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integrated-circuit description language") and Verilog.
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## Usage in _NAND to Tetris_
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We won't use an actual HDL language, instead we will use a simplified toy
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language called HDL that is simple enough that when it is used with a simulator,
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we can learn the main facets of chip design. Its syntax is very similar to VHDL.
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## Demonstration of HDL program
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### Boolean function to enact
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We will create an HDL program for an XOR gate that is implemented through the
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following arrangement of NOT, AND, and OR gates:
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### HDL file (`Xor.hdl`):
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Here is our HDL file:
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```
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/* Xor gate
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If a!=b out=1 else out=0
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*/
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CHIP Xor {
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IN a, b;
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OUT out;
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PARTS:
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Not (in=a, out=nota);
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Not (in=b, out=notb);
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And (a=a, b=notb, out=w1);
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And (a=nota, b=b, out=w2);
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Or (a=w1, b=w2, out=out)
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}
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```
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#### Interface (`CHIP, IN, OUT`)
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At the top level of the HDL program, the `CHIP` name and `IN`/`OUT` declaration
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is the _interface_ of the chip. Here we specify our naming convention for the
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`IN` and `OUT` values which we will refer to in the implementation declaration
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in `PARTS`.
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#### Implementation (`PARTS`)
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Everything under the `PARTS` section is the chip _implementation_. We can draw
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on composite gates in the `PARTS` declaration (e.g. `Not`, `And`, `Or`). The
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convention is to work from left to right when transcribing from a digital
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circuit diagram
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#### Pins
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In an HDL program we distinguish internal pins along with the standard
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[input and output pins](Integrated_circuits.md).
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At the level of the interface, we are concerned only with input and output pins
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(in the example program these are `a`, `b` and `out`). It is at the level of the
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implementation that internal pins are encountered. In the example these are the
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connections between, e.g. the AND and NOT gates such as
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`And (a=a, b-notb, out=w1)`. This means the AND gate is receiving through its
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`a` pin the input `a` value and through its `b` pin the value of `b` inverted by
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a NOT. `out` is the value that is computed based on the input pins of `a` and
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`b`.
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### Test file (`Xor.tst`)
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Along with the HDL file we also create a test file. This runs the chip against
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the inputs we supply, these will typically be equivalent to the (left-hand)
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truth-values column in a truth table which is the same as the parameters passed
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to a [Boolean function](Boolean_functions.md), for
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example:
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```vhdl
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load Xor.hdl
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output-list a, b, out;
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set a 0, set b 0, eval, output;
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set a 0, set b 1, eval, output;
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set a 1, set b 0, eval, output;
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set a 1, set b =, eval, output;
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```
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### Output file (`Xor.out`)
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When the test file is run against the HDL file it will generate an output file.
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This is effectively the result of the unit test. And will take the form of a
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truth table:
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```
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a | b | out
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-----------
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0 | 0 | 0
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0 | 1 | 1
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1 | 0 | 1
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1 | 1 | 0
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```
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