49 lines
2 KiB
Markdown
49 lines
2 KiB
Markdown
---
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tags:
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- binary
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- memory
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- electromagnetism
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- hardware
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---
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# Clock signals
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In the examples of digital circuits so far (i.e
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[adders](Half_adder_and_full_adder.md)
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and [latches](Latches.md)) everything
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happens in a single instant or over several repeated instances. This is because
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of how simple the circuits are. In the case of latches only a single bit is
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updated. And even with rippled adders they are just a series of 1-bit updaters
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in a chain.
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With more complex circuits that use multiple memory devices which store a series
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of bits at once, we need a way to ensure that the bits are set at the same time.
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We do this by sequencing the execution with the pulses of the system clock.
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A single iteration of the volatage rising and falling is a **pulse**. A complete
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oscillation from low to high and back to low is a **cycle**. As with all
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[electromagnetic](Electromagnetism.md)
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signals we measure the frequency of the wave in Hertz: cylcles per second. We
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also further distinguish the rising and falling edge of a pulse. Rising
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represents the signal passing from ground to its maximum voltage and falling is
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the reverse (the electrons moving from the voltage source to ground).
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The diagram below shows a pulse cycle of 2Hz.
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## Linking components to the clock
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- All components that need to be synchronised are connected to the clock
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- State changes in the component occur only when a clock pulse occurs
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- Clock-driven components will typically trigger their state changes on either
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the rising edge or the falling edge of the pulse.
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- Components that trigger state changes on the rising pulse are **positive
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edge-triggered**
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- Components that trigger state changes on the falling pulse are **negative
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edge-triggered**
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The role of the clock is essential in the functioning of the
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[CPU](CPU_architecture.md#the-system-clock). It is
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the system clock that gives CPUs their performance rating: how many processes
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can execute within a given clock cycle.
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