82 lines
3.1 KiB
Markdown
82 lines
3.1 KiB
Markdown
---
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categories:
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- Computer Architecture
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tags: [CPU]
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---
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# Fetch, decode, execute, store
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_Fetch, decode, execute_ is the operating cycle of the CPU. We will run through
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how this works with reference to the
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[CPU architecture](/Computer_Architecture/CPU/CPU_architecture.md).
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## Fetch
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### Overview
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First, instructions and data are fetched from outside of the CPU chip (usually
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from the DRAM). In some cases, the data used by an instruction will be included
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with it. In other instance the instruction will reference the location where the
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data are held as an address.
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### Specifics
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- The Program Counter register needs to keep track and sequence the different
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instructions that the CPU will work on. The first place it will look for an
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instruction is at the DRAM address `0000`, equivalent to 0 in the Program
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Counter register: the starting point. This is address therefore copied to the
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Memory Address Register for future reference.
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- This memory-storing event constitutes an instruction so it is copied to the
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Instruction Register.
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- As the first instruction has been fetched, the system reaches the end of the
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first cycle. Thus the Program counter increments by 1 to log this.
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- The next fetch cycle begins.
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## Decode
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### Overview
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Once the CPU has received the instruction, the CPU controller chip analyses it
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to determine which of its circuits should be used for processing.
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### Specifics
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- Now that the instruction is fetched and stored in the RAM it needs to be
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decoded. It is therefore sent from the RAM to the Control Unit of the CPU.
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There are two parts to the instruction:
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1. The operation code ("op code"): the command that the computer will carry
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out.
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1. The operand: an address in RAM where the data will be read and written to
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as part of the execution
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- The Control Unit converts the operation code and operand into an instruction
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that is fed to the next stage in the cycle: execution. For example, for an add
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function, `add` would be the op code and `address x` and `address y` would be
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the operands, thus the instruction would be: `add` the value in `address x` to
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the value in `address y`.
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## Execute
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Now the command will be executed. The operand is copied to the Memory Address
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Register and then passed to the Memory Data Register and the command is carried
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out by the ALU. The activities of ALU are covered in
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[CPU Architecture](/Computer_Architecture/CPU/CPU_architecture.md#arithmetic-logic-unit)
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and the notes on
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[Logic Gates](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md).
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## Store
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### Overview
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As well as telling the CPU what operation to perform, the instructions must
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specify where to store the result.
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### Specifics
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- Data is stored differently depending on the instruction.
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- If the instruction is iterative (e.g. adding two numbers and then multiplying
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by another number), the instruction will tell the CPU to store the interim
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first value in the CPU's
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[registers](/Computer_Architecture/CPU/CPU_architecture.md#registers). As
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these are part of the CPU, the data can be retrieved more readily. If the
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value is not expected to be used again immediately, it goes to the DRAM or
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harddisk.
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