50 lines
22 KiB
HTML
50 lines
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HTML
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<!--replace-end-7--><!--replace-end-4--><!--replace-end-1--></head><body><div class="ui fluid container universe"><!--replace-start-2--><!--replace-start-3--><!--replace-start-6--><div class="ui text container" id="zettel-container" style="position: relative"><div class="zettel-view"><article class="ui raised attached segment zettel-content"><div class="pandoc"><h1 id="title-h1">CPU architecture</h1><p>At the core of a computer sits the Central Processing Unit. This is the assembly of chips that execute all computation. Instructions are passed to the CPU along the data bus part of the <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Bus"><a href="Bus.html">system bus</a></span></span> from the memory. The <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: The kernel"><a href="The_kernel.html">kernel</a></span></span>, also residing in memory, sequences and schedules the sending of data to the CPU and manages requests from the CPU for data in memory.</p><p>The CPU comprises three core components:</p><ul><li>Registers (a type of memory positioned on the same chip as the CPU )</li><li>the Arithmetic Logic Unit (ALU)</li><li>the Control Unit (CU)</li></ul><p><img src="/static/von_neumann_architecture.jpeg" /></p><blockquote><p>This method of putting together a computer is known as the <strong>Von Neumann Architecture</strong>. It was devised by John von Neumann in about 1945, well before any of the components that would be needed to produce it had actually been invented.</p></blockquote><h2 id="registers">Registers</h2><p>This is the part of the CPU that stores data. The memory cells that comprise it do not have <span class="zettel-link-container errors"><span class="zettel-link" title="Wiki-link does not refer to any existing zettel"><a>Memory</a></span></span> (unlike RAM) so they cannot store very much data but they work faster, which is what is important. Because their memory capacity is so small, we measure the size of registers in bits rather than bytes.</p><p>In terms of speed, registers sit at the top part of the overall <a href="Memory.md#the-memory-hierarchy">memory hierarchy</a>.</p><p>There are five main types of register in the CPU:</p><table class="ui table"><thead><tr><th>Register type</th><th>What it stores</th></tr></thead><tbody><tr><td>Accumulator</td><td>The results of calculations</td></tr><tr><td>Instruction Register</td><td>The DRAM address of the <strong>instruction</strong> to be processed</td></tr><tr><td>Memory Address Register</td><td>The DRAM address of the <strong>data</strong> to be processed</td></tr><tr><td>Memory Data Register</td><td>The store of the data that is currently being processed</td></tr><tr><td>Program Counter</td><td>The RAM address of the <strong>next instruction</strong> to be processed</td></tr></tbody></table><h2 id="arithmetic-logic-unit">Arithmetic Logic Unit</h2><p>See <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Arithmetic Logic Unit (ALU)"><a href="Arithmetic_Logic_Unit.html">Arithmetic Logic Unit</a></span></span></p><h2 id="control-unit">Control Unit</h2><p>The CPU’s <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Chipset and controllers"><a href="Chipset_and_controllers.html">controller</a></span></span>. It takes the instructions in binary form from RAM memory (separate from the CPU, but connected) and then signals to the to ALU and memory registers what it is supposed to do to execute the instructions. Think of it as the overseer that gets the ALU and registers to work together to run program instructions.</p><h2 id="the-system-clock">The system clock</h2><p>Whilst modern CPUs and multithreading make it appear as though the CPU is capable of running multiple processes at once, access to the CPU is in fact sequential. The illusion of simultaneous computation is due to the fact the processor is so fast that we do not detect the sequential changes. For this to happen, the CPU needs to have a means of scheduling and sequencing processes. Thi
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