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<!--replace-end-7--><!--replace-end-4--><!--replace-end-1--></head><body><div class="ui fluid container universe"><!--replace-start-2--><!--replace-start-3--><!--replace-start-6--><div class="ui text container" id="zettel-container" style="position: relative"><div class="zettel-view"><article class="ui raised attached segment zettel-content"><div class="pandoc"><h1 id="title-h1">Logic gates</h1><blockquote><p>[A logic gate consists in] three connections where there may or may not be some electricity. Two of those connections are places where electricity may be put into the device, and the third connection is a place where electricity may come out of the device.</p></blockquote><p>[J.C. Scott. 2009. <strong>But How Do It Know? The Basics of Computers for Everyone</strong>, 21]</p><p>Logic gates are the basic building blocks of digital computing. <strong>A logic gate is an electrical circuit that has one or more than one input and only one output.</strong> The input and output points of the gate are <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Integrated circuits"><a href="Integrated_circuits.html">pins</a></span></span> The input controls the output and the logic determining which types of input (on/off) lead to specific outputs (on/off) is isomorphic with the truth-conditions of the <span class="zettel-link-container errors"><span class="zettel-link" title="Wiki-link does not refer to any existing zettel"><a>Truth-functional_connectives</a></span></span> specifiable in terms of <span class="zettel-link-container errors"><span class="zettel-link" title="Wiki-link does not refer to any existing zettel"><a>Truth-tables</a></span></span>.</p><p>Physically, what ‘travels through’ the gates is electrical current and what constitutes the ‘gate’ is a <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Transistors"><a href="Transistors.html">transistor</a></span></span> responding to the current. Going up a level of abstraction, the current/ charge is identified with a <a href="Binary_units_of_measurement.md#binary-units-of-measurement">bit</a>. It is bits that go into the gate and bits which come out: binary information that may be either 1 or 0.</p><h2 id="elementary-and-composite-gates">Elementary and composite gates</h2><p>We distinguish elementary from composite logic gates. An elementary gate is a single gate embodying a single logical connective. It cannot be reduced any lower as a logical abstraction. A composite gate is a gate made up of more than one elemen>tary gate and/or other composite gates.</p><p>An example of a composite gate would be a three-way AND. An AND with three inputs rather than the standard two that furnish the elementary AND gate. This gate would output 1 when all three gates have the value 1 and 0 otherwise. <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: The half adder and full adder"><a href="Half_adder_and_full_adder.html">Adders</a></span></span> and <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Latches"><a href="Latches.html">latche>s</a></span></span> whilst being <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Integrated circuits"><a href="Integrated_circuits.html">integrated circuits</a></span></span> are also, technically speaking, composite gates.</p><h2 id="gate-interface--gate-implementation">Gate interface / gate implementation</h2><p>The gate <em>interface</em> is an abstraction that the enables the user to think of the gate simply in terms of inputs and outputs, without being conc>erned with the technical details of how this is achieved. How it is achieved is the gate <em>implementation</em>.</p><p>We can demonstrate this with the earlier example of a three-way AND. The diagram below represents the gate as an interface:</p><p>// Add: Interface diagram</p><p>Whereas this diagram presents the implementation of the gate: it shows the specific combination of gates which creates the enables the behaviour represented in the interface diagram.</p><p>// Add: Implementation diagram</p><blockquote><p>Importantly, a single interface may be implemented in a variety of ways. There is a one-to-many relationship at work here. From the point of view of the user interface these differences should not be detectable. This is another example of <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Hardware abstraction and modularity"><a href="Hardware_abstraction_and_modularity.html">hardware abstraction</a></span></span></p></blockquote><h2 id="not-gate">NOT gate</h2><blockquote><p>The NOT gate inverts the value of whatever input it receives</p></blockquote><h3 id="truth-conditions">Truth conditions</h3><table class="ui table"><thead><tr><th><span class="math inline">\(P\)</span></th><th><span class="math inline">\(\lnot P\)</span></th></tr></thead><tbody><tr><td>1</td><td>0</td></tr><tr><td>0</td><td>1</td></tr></tbody></table><h3 id="interactive-circuit">Interactive circuit</h3><iframe src="https://circuitverse.org/simulator/embed/not-gate-aeb5f9e5-9f58-4883-b8e5-d70f6d023185?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginhe
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<h3 id="truth-conditions-1">Truth conditions</h3><p>tion) truth functional connective</p><h3 id="symbol">Symbol</h3><p><img src="/static/and-gate-new-2.png" /></p><h3 id="truth-conditions-2">Truth conditions</h3><h3 id="truth-conditions-3">Truth conditions</h3><p>| 1 | 0 | 0 | | 0 | 0 | 0 | | 0 | 0 | 0 |</p><h3 id="interactive-circuit-1">Interactive circuit</h3><iframe src="https://circuitverse.org/simulator/embed/and-gate-b6937338-e83f-474b-af79-854b39c151a3?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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<h2 id="nand-gate">NAND gate</h2><blockquote><p>The NAND gate inverts the truth conditions of AND.</p></blockquote><h3 id="symbol-1">Symbol</h3><p><img src="/static/nand-gate-new.png" /></p><h3 id="truth-conditions-4">Truth conditions</h3><table class="ui table"><thead><tr><th><span class="math inline">\(P\)</span></th><th><span class="math inline">\(Q\)</span></th><th><span class="math inline">\(\lnot(P \land Q)\)</span></th></tr></thead><tbody><tr><td>1</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>0</td><td>0</td><td>1</td></tr></tbody></table><h3 id="interactive-circuit-2">Interactive circuit</h3><iframe src="https://circuitverse.org/simulator/embed/nand-gate-60613ab9-9562-445e-9883-c4ea1920e206?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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<p>NAND is a <strong>universal logic gate</strong>: equipped with just a NAND we can represent every other possible logical condition. In practice with circuits, it is more efficient to use specific dedicated gates (i.e OR, AND, NOT etc) for the other Boolean connectives but in principle the same output can be achieved through NANDs alone.</p><h2 id="or-gate">OR gate</h2><blockquote><p>The OR gate represents the truth conditions of the [disjunction](Truth-functional_connectives<span><code class="inline-tag">###</code></span> Truth conditions.md<span><code class="inline-tag">#disjunction)</code></span> truth functional connective</p></blockquote><h3 id="symbol-2">Symbol</h3><p><img src="/static/or-gate-new.png" /></p><h3 id="truth-condition">Truth condition</h3><h3 id="truth-conditions-5">Truth conditions</h3><p>s</p><table class="ui table"><thead><tr><th><span class="math inline">\(P\)</span></th><th><span class="math inline">\(Q\)</span></th><th><span class="math inline">\(P \lor Q\)</span></th></tr></thead><tbody><tr><td>1</td><td>1</td><td>1</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>0</td><td>0</td><td>0</td></tr></tbody></table><h3 id="interactive-circui">Interactive circui</h3><h3 id="truth-conditions-6">Truth conditions</h3><p>t</p><iframe src="https://circuitverse.org/simulator/embed/or-gate-087e4933-7963-482d-b4bf-9e130ef05706?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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<h2 id="xor-gate">XOR gate</h2><blockquote><p>The OR gate represents the truth conditions of the exclusive OR</p></blockquote><h3 id="symbol-3">Symbol</h3><p><img src="/static/xor-gate-new.png" /></p><h3 id="truth-conditions-7">Truth conditions</h3><table class="ui table"><thead><tr><th><span class="math inline">\(P\)</span></th><th><span class="math inline">\(Q\)</span></th><th><span class="math inline">\(\lnot(P \Leftrightarrow Q)\)</span></th></tr></thead><tbody><tr><td>1</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>1</td></tr><tr><td>0</td><td>1</td><td>1</td></tr><tr><td>0</td><td>0</td><td>0</td></tr></tbody></table><h3 id="interactive-circuit-3">Interactive circuit</h3><iframe src="https://circuitverse.org/simulator/embed/xor-gate-a240131e-a9c3-4240-a52b-e14412fdd654?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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<h2 id="nor-gate">NOR gate</h2><blockquote><p>The NOR gate inverts the function of an OR gate</p></blockquote><h3 id="symbol-4">Symbol</h3><p><img src="/static/nor-gate-new.png" /></p><h3 id="truth-conditions-8">Truth conditions</h3><table class="ui table"><thead><tr><th><span class="math inline">\(P\)</span></th><th><span class="math inline">\(Q\)</span></th><th><span class="math inline">\(P \lor Q\)</span></th></tr></thead><tbody><tr><td>1</td><td>1</td><td>0</td></tr><tr><td>1</td><td>0</td><td>0</td></tr><tr><td>0</td><td>1</td><td>0</td></tr><tr><td>0</td><td>0</td><td>1</td></tr></tbody></table><h3 id="interactive-circuit-4">Interactive circuit</h3><iframe src="https://circuitverse.org/simulator/embed/nor-gate-ac7946b4-f5d0-4c87-afd1-a2e92326d006?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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</div></article><nav class="ui attached segment deemphasized backlinksPane" id="neuron-backlinks-pane"><h3 class="ui header">Backlinks</h3><ul class="backlinks"><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Half_adder_and_full_adder.html">The half adder and full adder</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>The half adder and full adder are components of digital circuits that enable us to carry out binary addition. Using adders and half adders we can add two binary numbers together. Adders are a type of <a>integrated circuit</a> comprising certain <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">logic gates</a></span></span> where the arrangement allows for the representation of the addition of bits.</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Fetch_decode_execute.html">Fetch, decode, execute, store</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>Now the command will be executed. The operand is copied to the Memory Address Register and then passed to the Memory Data Register and the command is carried out by the ALU. The activities of ALU are covered in <a href="CPU_architecture.md#arithmetic-logic-unit">CPU Architecture</a> and the notes on <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">Logic Gates</a></span></span>.</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="CPU_architecture.html">CPU architecture</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>The clock’s circuitry is based on a quartz crystal system like that used in watches. At precisely timed intervals, the clock sends out pulses of electricity that cause bits to move from place to place within <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">logic gates</a></span></span> or between logic gates and <a href="CPU_architecture.md#registers">registers</a>. This is covered in greater detail in the discussion of <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Clock signals"><a href="Clock_signals.html">clock signals in digital circuits</a></span></span>.</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Boolean_function_synthesis.html">Boolean function synthesis</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>This is an important skill that we will use when constructing <span class="zettel-link-container errors"><span class="zettel-link" title="Wiki-link does not refer to any existing zettel"><a>Digital_circuits</a></span></span>. We will go from truth conditions (i.e. what we want the circuit to do and when we want it to do it) to a function expression which is then reduced to its simplest form and implemented with <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">logic gates</a></span></span>. Specifically, NAND gates.</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Boolean_algebra.html">Boolean algebra</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>The fact that we can take a complex Boolean function and reduce it to a simpler formulation has great significance for the development of computer architectures, specifically <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">logic gates</a></span></span>. It would be rather resource intensive and inefficient to create a gate that is representative of the complex function. Whereas the simplified version only requires a single <a href="Logic_gates.md#or-gate">OR gate</a>.</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Arithmetic_Logic_Unit.html">Arithmetic Logic Unit (ALU)</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>The ALU comprises <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">logic gates</a></span></span> that execute the instructions passed from memory and where the data stored by the registers is acted upon. A processor’s ALU is just a complex combinatorial logic circuit.</p></div></li></ul></li></ul></nav><nav class="ui attached segment deemphasized bottomPane" id="neuron-tags-pane"><div><span class="ui basic label zettel-tag" title="Tag">##</span><span class="ui basic label zettel-tag" title="Tag">binary</span><span class="ui basic label zettel-tag" title="Tag">disjunction)</span><span class="ui basic label zettel-tag" title="Tag">logic-gates</span></div></nav><nav class="ui bottom attached icon compact inverted menu blue" id="neuron-nav-bar"><!--replace-start-9--><!--replace-end-9--><a class="right item" href="impulse.html" title="Open Impulse"><i class="wave square icon"></i></a></nav></div></div><!--replace-end-6--><!--replace-end-3--><!--replace-end-2--><div class="ui center aligned container footer-version"><div class="ui tiny image"><a href="https://neuron.zettel.page"><img alt="logo" src="https://raw.githubusercontent.com/srid/neuron/master/assets/neuron.svg" title="Generated by Neuron 1.9.35.3" /></a></div></div></div></body></html> |