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<!--replace-end-7--><!--replace-end-4--><!--replace-end-1--></head><body><div class="ui fluid container universe"><!--replace-start-2--><!--replace-start-3--><!--replace-start-6--><div class="ui text container" id="zettel-container" style="position: relative"><div class="zettel-view"><article class="ui raised attached segment zettel-content"><div class="pandoc"><h1 id="title-h1">Four-bit adder</h1><p>A single <a href="Half_adder_and_full_adder.md#half-adder">half adder</a> and <a href="Half_adder_and_full_adder.md#fufll-adder">full adder</a> allows us to calculate the sum of two 1-bit numbers, but this is not much use in practice. To approximate what is really happening at the circuit level in computers we need to be able to add bigger binary numbers. We will demonstrate how this can be achieved for a four-bit number (nibble) using repeated full adders and half adders.</p><p>We want to be able to calculate the following sum:</p><pre><code class="language-none">0010
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0011
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____
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0101</code></pre><p>We will achieve this by using three full adders and one half adder, moving from right to left. The half adder will be used at the beginning to calculate the least significant bit as it will have no carry-in. The subsequent three bits will all be added using a full adder.</p><p>Let’s walk through the process:</p><blockquote></blockquote><ol><li>HA receives the bits <span class="math inline">\(0\)</span> and <span class="math inline">\(1\)</span> as inputs. It outputs <span class="math inline">\(1\)</span> as the sum bit and <span class="math inline">\(0\)</span> as the carry-out.</li><li>FA1 receives <span class="math inline">\(0\)</span> as the carry-in bit plus <span class="math inline">\(1\)</span> and <span class="math inline">\(1\)</span> as its input. This means it has the following calculation to execute: <span class="math inline">\(1 + 1 + 0\)</span>. This gives <span class="math inline">\(0\)</span> as the sum bit and <span class="math inline">\(1\)</span> as the carry-out bit.</li><li>FA2 receives <span class="math inline">\(1\)</span> as the carry-in (the carry-out from FA1) plus <span class="math inline">\(0\)</span> and <span class="math inline">\(0\)</span> as its own inputs. <span class="math inline">\(0 + 0 + 1\)</span> gives us <span class="math inline">\(1\)</span> as the sum bit and <span class="math inline">\(0\)</span> as the carry-out.</li><li>Finally FA3 receives <span class="math inline">\(0\)</span> as its carry-in plus <span class="math inline">\(0\)</span> and <span class="math inline">\(0\)</span> as its inputs. <span class="math inline">\(0 + 0 + 0 = 0\)</span>, therefore its sum bit is <span class="math inline">\(0\)</span> and the overall sum of the four bits is <span class="math inline">\(0101\)</span>. There is no carry out as there are no more bits to add.</li></ol><h2 id="ripple-carry-adder">Ripple carry adder</h2><p>We notice that as the calculation proceeds, the carry bits propagate or <em>ripple</em> through the circuit. For this reason, a four-bit adder constructed in the manner of this circuit is called a <strong>ripple carry adder</strong>.</p><p>There are two important consequences to note about this type of circuit:</p><ul><li>Each carry bit that ripples to the next full adder introduces a small delay. Therefore extending the circuit to handle more bits will make the circuit slower overall.</li><li>Because the value of the bits changes through the course of the ripple, the output of the circuit will be innacurate until all the carry bits have had time to propagate.</li></ul></div></article><nav class="ui attached segment deemphasized bottomPane" id="neuron-tags-pane"><div><span class="ui basic label zettel-tag" title="Tag">binary</span><span class="ui basic label zettel-tag" title="Tag">logic-gates</span></div></nav><nav class="ui bottom attached icon compact inverted menu blue" id="neuron-nav-bar"><!--replace-start-9--><!--replace-end-9--><a class="right item" href="impulse.html" title="Open Impulse"><i class="wave square icon"></i></a></nav></div></div><!--replace-end-6--><!--replace-end-3--><!--replace-end-2--><div class="ui center aligned container footer-version"><div class="ui tiny image"><a href="https://neuron.zettel.page"><img alt="logo" src="https://raw.githubusercontent.com/srid/neuron/master/assets/neuron.svg" title="Generated by Neuron 1.9.35.3" /></a></div></div></div></body></html> |