From cae130dc0864a433f9290ffa6c6ae8b5af9cafd7 Mon Sep 17 00:00:00 2001
From: thomasabishop <tactonbishop@gmail.com>
Date: Wed, 18 Jan 2023 19:52:45 +0000
Subject: [PATCH] update

---
 .../Digital_circuits/Four_bit_adder.md        |   2 +-
 .../Digital_circuits/Latches.md               |   8 ++--
 .../Digital_circuits/Logic_gates.md           |  39 ++++++++++--------
 Linux/Procedural/Save_readonly_Vim_file.md    |  12 ++++++
 Linux/journald.md                             |   2 +-
 _img/four-bit-adder.png                       | Bin 21314 -> 0 bytes
 _img/not-gate-new.png                         | Bin 2705 -> 0 bytes
 7 files changed, 39 insertions(+), 24 deletions(-)
 create mode 100644 Linux/Procedural/Save_readonly_Vim_file.md
 delete mode 100644 _img/four-bit-adder.png
 delete mode 100644 _img/not-gate-new.png

diff --git a/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md b/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md
index 17c90ee..a518805 100644
--- a/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md
+++ b/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md
@@ -22,7 +22,7 @@ We will achieve this by using three full adders and one half adder, moving from
 
 Let's walk through the process:
 
-![](/_img/four-bit-adder.png)
+>
 
 1. HA receives the bits $0$ and $1$ as inputs. It outputs $1$ as the sum bit and $0$ as the carry-out.
 2. FA1 receives $0$ as the carry-in bit plus $1$ and $1$ as its input. This means it has the following calculation to execute: $1 + 1 + 0$. This gives $0$ as the sum bit and $1$ as the carry-out bit.
diff --git a/Electronics_and_Hardware/Digital_circuits/Latches.md b/Electronics_and_Hardware/Digital_circuits/Latches.md
index ef68754..c94a900 100644
--- a/Electronics_and_Hardware/Digital_circuits/Latches.md
+++ b/Electronics_and_Hardware/Digital_circuits/Latches.md
@@ -14,7 +14,7 @@ In contrast, the output of a **sequential digital circuit** depends not only on
 
 ## What is a latch?
 
-A latch is a circuit component that works as a very basic memory device. It is capable of setting and resetting a single bit. We can remember what it does by thinking of a door latch: once you turn the key the lock is set, when you turn it back it is unset.
+A latch is a circuit component that wor
 
 The **SR Latch** (for "set/reset") has two inputs: _S_ (for "set") and _R_ (for "reset") and one output, _Q_. _Q_ stands for the bit that is remembered. (There is also _not-Q_ which is the opposite of whatever _Q_ is currently set to.)
 
@@ -27,9 +27,9 @@ The SR Latch goes through the following state changes:
 
 This is represented more clearly in the table below:
 
-| S | R | Q | Operation |
-| --- | --- | ----------------------- | ---------<iframe src="https://circuitverse.org/simulator/embed/multiplexor-5406f205-8ac7-4c5b-a1ba-861c5face8d3?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="500" width="500" allowFullScreen></iframe> |
-| 1 | 1 | X | Invalid, null |
+| S   | R   | Q   | Operation     |
+| --- | --- | --- | ------------- |
+| 1   | 1   | X   | Invalid, null |
 
 The most succinct account of a latch:
 
diff --git a/Electronics_and_Hardware/Digital_circuits/Logic_gates.md b/Electronics_and_Hardware/Digital_circuits/Logic_gates.md
index 9a99440..daadcf1 100644
--- a/Electronics_and_Hardware/Digital_circuits/Logic_gates.md
+++ b/Electronics_and_Hardware/Digital_circuits/Logic_gates.md
@@ -18,13 +18,13 @@ Physically, what 'travels through' the gates is electrical current and what cons
 
 ## Elementary and composite gates
 
-We distinguish elementary from composite logic gates. An elementary gate is a single gate embodying a single logical connective. It cannot be reduced any lower as a logical abstraction. A composite gate is a gate made up of more than one elementary gate and/or other composite gates.
+We distinguish elementary from composite logic gates. An elementary gate is a single gate embodying a single logical connective. It cannot be reduced any lower as a logical abstraction. A composite gate is a gate made up of more than one elemen>tary gate and/or other composite gates.
 
-An example of a composite gate would be a three-way AND. An AND with three inputs rather than the standard two that furnish the elementary AND gate. This gate would output 1 when all three gates have the value 1 and 0 otherwise. [Adders](/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md) and [latches](/Electronics_and_Hardware/Digital_circuits/Latches.md) whilst being [integrated circuits](/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md) are also, technically speaking, composite gates.
+An example of a composite gate would be a three-way AND. An AND with three inputs rather than the standard two that furnish the elementary AND gate. This gate would output 1 when all three gates have the value 1 and 0 otherwise. [Adders](/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md) and [latche>s](/Electronics_and_Hardware/Digital_circuits/Latches.md) whilst being [integrated circuits](/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md) are also, technically speaking, composite gates.
 
 ## Gate interface / gate implementation
 
-The gate _interface_ is an abstraction that the enables the user to think of the gate simply in terms of inputs and outputs, without being concerned with the technical details of how this is achieved. How it is achieved is the gate _implementation_.
+The gate _interface_ is an abstraction that the enables the user to think of the gate simply in terms of inputs and outputs, without being conc>erned with the technical details of how this is achieved. How it is achieved is the gate _implementation_.
 
 We can demonstrate this with the earlier example of a three-way AND. The diagram below represents the gate as an interface:
 
@@ -32,7 +32,7 @@ We can demonstrate this with the earlier example of a three-way AND. The diagram
 
 Whereas this diagram presents the implementation of the gate: it shows the specific combination of gates which creates the enables the behaviour represented in the interface diagram.
 
-// TODO: Implementation diagram
+// TODO: Implementation diagra>m
 
 > Importantly, a single interface may be implemented in a variety of ways. There is a one-to-many relationship at work here. From the point of view of the user interface these differences should not be detectable. This is another example of [hardware abstraction](/Computer_Architecture/Hardware_abstraction_and_modularity.md)
 
@@ -40,10 +40,6 @@ Whereas this diagram presents the implementation of the gate: it shows the speci
 
 > The NOT gate inverts the value of whatever input it receives
 
-### Symbol
-
-![](/_img/not-gate-new.png)
-
 ### Truth conditions
 
 | $P$ | $\lnot P$ |
@@ -53,11 +49,11 @@ Whereas this diagram presents the implementation of the gate: it shows the speci
 
 ### Interactive circuit
 
-<iframe src="https://circuitverse.org/simulator/embed/not-gate-aeb5f9e5-9f58-4883-b8e5-d70f6d023185?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
+<iframe src="https://circuitverse.org/simulator/embed/not-gate-aeb5f9e5-9f58-4883-b8e5-d70f6d023185?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginhe
 
-## AND gate
+### Truth conditions
 
-> The AND gate represents the truth conditions of the [conjunction](/Logic/Truth-functional_connectives.md#conjunction) truth functional connective
+tion) truth functional connective
 
 ### Symbol
 
@@ -65,12 +61,11 @@ Whereas this diagram presents the implementation of the gate: it shows the speci
 
 ### Truth conditions
 
-| $P$ | $Q$ | $P \land Q$ |
-| --- | --- | ----------- |
-| 1   | 1   | 1           |
-| 1   | 0   | 0           |
-| 0   | 0   | 0           |
-| 0   | 0   | 0           |
+### Truth conditions
+
+| 1 | 0 | 0 |
+| 0 | 0 | 0 |
+| 0 | 0 | 0 |
 
 ### Interactive circuit
 
@@ -107,8 +102,12 @@ NAND is a **universal logic gate**: equipped with just a NAND we can represent e
 
 ![](/_img/or-gate-new.png)
 
+### Truth condition
+
 ### Truth conditions
 
+s
+
 | $P$ | $Q$ | $P \lor Q$ |
 | --- | --- | ---------- |
 | 1   | 1   | 1          |
@@ -116,7 +115,11 @@ NAND is a **universal logic gate**: equipped with just a NAND we can represent e
 | 0   | 1   | 1          |
 | 0   | 0   | 0          |
 
-### Interactive circuit
+### Interactive circui
+
+### Truth conditions
+
+t
 
 <iframe src="https://circuitverse.org/simulator/embed/or-gate-087e4933-7963-482d-b4bf-9e130ef05706?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
 
diff --git a/Linux/Procedural/Save_readonly_Vim_file.md b/Linux/Procedural/Save_readonly_Vim_file.md
new file mode 100644
index 0000000..3447be8
--- /dev/null
+++ b/Linux/Procedural/Save_readonly_Vim_file.md
@@ -0,0 +1,12 @@
+---
+categories:
+  - Linux
+  - Networks
+tags: []
+---
+
+# Save read only Vim file
+
+```
+ :w !sudo tee % >/dev/null
+```
diff --git a/Linux/journald.md b/Linux/journald.md
index fffaa62..6ec9d32 100644
--- a/Linux/journald.md
+++ b/Linux/journald.md
@@ -31,7 +31,7 @@ journalctl -S -1h
 ### View logs for a specfic systemd unit
 
 ```bash
-journalctl -u cronie.service
+journalctl -u [unit_name] -e
 ```
 
 ### View boot logs
diff --git a/_img/four-bit-adder.png b/_img/four-bit-adder.png
deleted file mode 100644
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GIT binary patch
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