Autosave: 2022-12-12 07:53:34

Electronics_and_Hardware/Digital_circuits/Clock_signals.md

@@ -3,7 +3,7 @@ categories:
   - Computer Architecture
   - Electronics
   - Hardware
-tags: [logic-gates, binary, memory, clock, electromagnetism]
+tags: [binary, memory, clock, electromagnetism]
 ---
 
 # Clock signals
@@ -26,7 +26,12 @@ The diagram below shows a pulse cycle of 2Hz.
 
 - All components that need to be synchronised are connected to the clock
 - State changes in the component occur only when a clock pulse occurs
-- Clock-driven components will typically trigger their state changes on either the rising edge or the falling edge of the pulse.
+- Clock-driven components will typically trigger their state c| J 	| K 	| Clock 	| Q state                   	| Operation 	|
+|---	|---	|-------	|---------------------------	|-----------	|
+| 0 	| 0 	| Pulse 	| Maintain previous value   	| Hold      	|
+| 0 	| 1 	| Pulse 	| 0                         	| Reset     	|
+| 1 	| 0 	| Pulse 	| 1                         	| Set       	|
+| 1 	| 1 	| Pulse 	| Inverse of previous value 	| Toggle    	|hanges on either the rising edge or the falling edge of the pulse.
 - Components that trigger state changes on the rising pulse are **positive edge-triggered**
 - Components that trigger state changes on the falling pulse are **negative edge-triggered**
 

Electronics_and_Hardware/Digital_circuits/Flip_flops.md

@@ -13,7 +13,7 @@ A flip-flop is a type of [latch](/Electronics_and_Hardware/Digital_circuits/Latc
 
 The JK Flip-Flop (the letters are meaningless) is basically an SR latch in functionality. It has a "set" input (_J_) and a "reset" input (_K_) and _Q_ and inverted-_Q_ outputs.
 
-Where it differs from the SR is that it the SR will change state just if the voltage is high (this, afterall, is all that a bit is) whereas for the JK to set it **must receive a clock pulse** and it will only set on the pulse. 
+Where it differs from the SR is that it the SR will change state just if the voltage is high (this, afterall, is all that a bit is) whereas for the JK to set it **must receive a clock pulse** and it will only set on the pulse. Hence in addition to _J_ and _K_ inputs it has a _CLK_ input for "clock".
 
 In addition the JK Flip-Flop has a **toggle** function. When this is executed, whatever _Q_ currently is will be flipped to its opposite value: $1 \rightarrow 0$,  $0 \rightarrow 1$. The toggle executes when both _J_ and _K_ are set to high.
 
@@ -29,3 +29,16 @@ The possible state changes for the JK Flip-Flop are detailed below:
 A JK Flip-Flop can execute on either the positive or negative pulse. Below are the diagrams fora rising and falling pulse respectively:
 
 // TODO diagram of JK Flipflop 
+
+## T Flip-Flops
+
+Another type of Flip-Flop can be created by connecting the _J_ and _K_ inputs of a JK Flip-Flop to each other. This reduces the possible states to two: toggle current state or maintain current state. Its overall logic is therefore reduced to just two lines of the previous state table: the state that obtains when _J_ and _K_ are $0 0$ or $1 1$. 
+
+Thus the state table for the T Flip-Flop is:
+
+| T 	| Clock 	| Q state                   	| Operation 	|
+|---	|-------	|---------------------------	|-----------	|
+| 0 	| Pulse 	| Maintain previous value   	| Hold      	|
+| 0 	| Pulse 	| Inverse of previous value 	| Toggle    	|
+
+// TODO: Add diagram

Electronics_and_Hardware/Digital_circuits/Three_bit_counter.md

@@ -0,0 +1,23 @@
+---
+categories:
+  - Electronics
+  - Hardware
+tags: [logic-gates, binary, memory, clock]
+---
+
+# 3-bit Counter
+
+To demonstrate the use of [Flip-Flops](/Electronics_and_Hardware/Digital_circuits/Flip_flops.md) we will create the circuit for a 3-bit counter. This simply counts up from 0 to 7 because 7 is the maximum decimal number we can create with three bits ($2^3$): 
+
+| Binary 	| Decimal 	| 
+|-------	| -------	|
+| 000 	    | 0	        | 
+| 001 	    | 1 	    | 
+| 010 	    | 2 	    | 
+| 011	    | 3 	    | 
+| 100 	    | 4 	    | 
+| 101 	    | 5 	    | 
+| 110 	    | 6 	    | 
+| 111 	    | 7 	    | 
+
+The circuit will have three memory components, each representing one bit of the 3-bit number. When the clock pulses, the 3-bit number increments by one. We need to synchronise the operation with a clock because each bit by itself is meaningless, it only gains meaning by the relation it sustains to the other two bits hence it must be kept in sync with them.