diff --git a/Hardware/Memory/RAM_types.md b/Hardware/Memory/RAM_types.md
index f1d8310..f311500 100644
--- a/Hardware/Memory/RAM_types.md
+++ b/Hardware/Memory/RAM_types.md
@@ -26,6 +26,14 @@ SRAM (Static Random Access Memory) is also volatile memory but, in terms of the
 ### Relative speeds
 The table below details the relative speeds of the different types of memory and those of other types of motherboard storage.
 
+| Storage type | Access speed (clock cycles) | Relative times slower |
+|--------------|-----------------------------|-----------------------|
+| CPU register | 2                           |                       |
+| L1 cache     | 4                           | 2x                    |
+| L2 cache     | 6-20                        | 3-10x                 |
+| DRAM memory  | 50                          | 25x                   |
+| Harddisk     | 2000                        | 1000x                 |
+
 
 ## References
 
diff --git a/Hardware/Memory/Role_in_computation.md b/Hardware/Memory/Role_in_computation.md
index c164304..b17a4bb 100644
--- a/Hardware/Memory/Role_in_computation.md
+++ b/Hardware/Memory/Role_in_computation.md
@@ -15,6 +15,8 @@ The following steps outline the way in which memory interacts with the processor
 
 > This is a simplified account; it is not the case that only single requests are passed back and forth. This would be inefficient and time-wasting. The kernel sends to the CPU not just the first instruction in the requested file but also a number of instructions that immediately follow it. 
 
+![](/img/memory-flow.svg)
+
 Every part of the above process - the journey accross the bus, the lookup in the controller, the operations on the DRAM, the journey back accross the bus - takes muliple CPU clock cycles. 
 
 ## The role of the cache