Autosave: 2022-12-11 13:30:05

Computer_Architecture/CPU/CPU_architecture.md

@@ -56,9 +56,9 @@ The CPU's [controller](/Hardware/Chipset_and_controllers.md). It takes the instr
 
 ## The system clock
 
-Whilst modern CPUs and multithreading make it appear[] as though the CPU is capable of running multiple processes at once, access to the CPU is in fact sequential. The illusion of simultaneous computation is due to the fact the processor is so fast that we do not detect the sequential changes. For this to happen, the CPU needs to have a means of scheduling and sequencing processes. This is made possible through the system clock, hence when talking about the speed of the CPU we do so with reference to _clock speeds_ and the _clock cycle_.
+Whilst modern CPUs and multithreading make it appear as though the CPU is capable of running multiple processes at once, access to the CPU is in fact sequential. The illusion of simultaneous computation is due to the fact the processor is so fast that we do not detect the sequential changes. For this to happen, the CPU needs to have a means of scheduling and sequencing processes. This is made possible through the system clock, hence when talking about the speed of the CPU we do so with reference to _clock speeds_ and the _clock cycle_.
 
-The clock's circuitry is based on a quartz crystal system like that used in watches. At precisely timed intervals, the clock sends out pulses of electricity that cause bits to move from place to place within [logic gates](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md) or between logic gates and [registers](/Computer_Architecture/CPU/CPU_architecture.md#registers).
+The clock's circuitry is based on a quartz crystal system like that used in watches. At precisely timed intervals, the clock sends out pulses of electricity that cause bits to move from place to place within [logic gates](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md) or between logic gates and [registers](/Computer_Architecture/CPU/CPU_architecture.md#registers). This is covered in greater detail in the discussion of [clock signals in digital circuits](/Electronics_and_Hardware/Digital_circuits/Clock_signals.md)
 
 Simple instructions such as add can often be executed in just one clock cycle, whilst complex operations such as divide will require a number of smaller steps, each using one cycle.
 

Electronics_and_Hardware/Digital_circuits/Clock_signals.md

@@ -16,7 +16,7 @@ We synchronize multiple circuit components with a **clock signal**.
 
 A clock signal alternates its voltage level from high to low on a regular cadence where it is high half the time and low the rest of the time. This gives the wave form a squared appearence.
 
-A single iteration of the volatage rising and falling is a **pulse**. A complete oscillation from low to high and back to low is a **cycle**. As with all [electromagnetic]() signals we measure the frequency of the wave in Hertz: cylcles per second. We also further distinguish the rising and falling edge of a pulse. Rising represents the signal passing from ground to its maximum voltage and falling is the reverse (the electrons moving from the voltage source to ground).
+A single iteration of the volatage rising and falling is a **pulse**. A complete oscillation from low to high and back to low is a **cycle**. As with all [electromagnetic](/Electronics_and_Hardware/Physics_of_electricity/Electromagnetism.md) signals we measure the frequency of the wave in Hertz: cylcles per second. We also further distinguish the rising and falling edge of a pulse. Rising represents the signal passing from ground to its maximum voltage and falling is the reverse (the electrons moving from the voltage source to ground).
 
 The diagram below shows a pulse cycle of 2Hz.
 
@@ -29,3 +29,5 @@ The diagram below shows a pulse cycle of 2Hz.
 - Clock-driven components will typically trigger their state changes on either the rising edge or the falling edge of the pulse.
 - Components that trigger state changes on the rising pulse are **positive edge-triggered**
 - Components that trigger state changes on the falling pulse are **negative edge-triggered**
+
+The role of the clock is essential in the functioning of the [CPU](/Computer_Architecture/CPU/CPU_architecture.md#the-system-clock). It is the system clock that gives CPUs their performance rating: how many processes can execute within a given clock cycle.