Autosave: 2022-12-31 12:00:05

Computer_Architecture/Hardware_simulation.md

@@ -6,3 +6,13 @@ tags: [HDL, nand-to-tetris]
 ---
 
 # Hardware simulation
+
+In order to test our [HDL](/Computer_Architecture/Hardware_Description_Language.md) files we load them into the hardware simulator program shown below:
+
+<img src="/home/thomas/repos/computer_science/_img/hardware-simulator.png" width="500">
+
+There are several simulation options:
+
+- interactive
+- script-based (where we load a test script into the simulator along with the HDL file
+- comparative (running the HDL program against our intended output specified in the `.out` file)

Electronics_and_Hardware/Digital_circuits/Clock_signals.md

@@ -26,12 +26,7 @@ The diagram below shows a pulse cycle of 2Hz.
 
 - All components that need to be synchronised are connected to the clock
 - State changes in the component occur only when a clock pulse occurs
-- Clock-driven components will typically trigger their state c| J 	| K 	| Clock 	| Q state                   	| Operation 	|
-|---	|---	|-------	|---------------------------	|-----------	|
-| 0 	| 0 	| Pulse 	| Maintain previous value   	| Hold      	|
-| 0 	| 1 	| Pulse 	| 0                         	| Reset     	|
-| 1 	| 0 	| Pulse 	| 1                         	| Set       	|
-| 1 	| 1 	| Pulse 	| Inverse of previous value 	| Toggle    	|hanges on either the rising edge or the falling edge of the pulse.
+- | Clock-driven components will typically trigger their state changes on either the rising edge or the falling edge of the pulse. |
 - Components that trigger state changes on the rising pulse are **positive edge-triggered**
 - Components that trigger state changes on the falling pulse are **negative edge-triggered**