Autosave: 2022-12-10 11:00:04

Electronics/Digital_Circuits/Latches.md

@@ -34,7 +34,9 @@ This is represented more clearly in the table below:
 | 1   | 0   | 1                       | Set           |
 | 1   | 1   | X                       | Invalid, null |
 
-Important to note that this works if we set 1 or 0 as the bit to be remembered, not just if S is set to 1. Either way, the remembered bit will be represented by _Q_ regardless of how many times we toggle _S_ after the initial setting.
+The most succinct account of a latch:
+
+> A latch is a 1-bit memory device that has a state _Q_ of either 1 or 0. The _S_ input sets _Q_ to 1 and the _R_ input resets _Q_ to 0.
 
 _The representation of an SR Latch in a digital circuit diagram_:
 
@@ -42,14 +44,16 @@ _The representation of an SR Latch in a digital circuit diagram_:
 
 ## Creating a latch circuit
 
-There is more than one way of implementing a latch with logic gates. We will look at two formulations which both use a single type of gate: [NANDs](/Hardware/Logic_Gates/Logic_gates.md#nand-gate) and [NORs](/Hardware/Logic_Gates/Logic_gates.md#nor-gate) (both universal logic gates).
+The circuit diagram latch symbol obviously encapsulates more complex functionality that occurs at the sub-circuit level. We will demonstrate how this functionality can be achieved with two [NOR](/Hardware/Logic_Gates/Logic_gates.md#nor-gate) gates.
 
-In each case, the gates are in a **cross-coupled configuration**. This basically means that the wires are crossed back on themselves such that the output of one is also an input of the other at a single stage in the sequence.
+The two gates are in a **cross-coupled configuration**. This basically means that the wires are crossed back on themselves such that the output of one is also an input of the other at a single stage in the sequence.
 
-### NOR latch
+The circuit is created as follows:
 
 ![](/img/sr_latch_logic_circuit.png)
 
+Interactive version:
+
 <iframe src="https://circuitverse.org/simulator/embed/nor-latch-0869192c-7d7b-4161-b13f-3f72c1bce8e9" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="400" width="600" allowFullScreen></iframe>
 
 <br />
@@ -67,10 +71,3 @@ Let's talk through the logic at each state change:
 - _Q_ remains at 0 even if _R_ goes back to 0
   - N2 is receiving 0 as its bottom input from R and 1 as its top input from N1. TF equals F in NOR hence the output of N2 is 0 and Q remains 0
   - N1 is outputting 1 because it is receiving 0 as its top input from S and 0 as its bottom input from N2. FF equals T in NOR hence N1 is 1
-
-### NAND latch
-
-With a NAND-based memory implementation we have two inputs: _I_ which is the bit we want to store in memory and _S_ which sets it. There is a single output _O_ which  
-![](/img/nand_latch_logic_circuit.png)
-
-<iframe src="https://circuitverse.org/simulator/embed/nand-mem?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="500" width="600" allowFullScreen></iframe>

Hardware/Logic_Gates/Creating_memory_with_NAND.md

@@ -11,8 +11,7 @@ tags: [logic-gates, binary, memory]
 
 The [logic circuit](/Hardware/Logic_Gates/Logic_circuits.md) below demonstrates how memory can be created using [NAND](/Hardware/Logic_Gates/Nand_gate.md) gates. A single bit is stored in memory.
 
-![](/img/nand-memory.svg)
-
+![](/img/nand_latch_logic_circuit.png)
 Interactive version of circuit:
 
 <iframe src="https://circuitverse.org/simulator/embed/nand-mem?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="500" width="500" allowFullScreen></iframe>

Hardware/Logic_Gates/Not_gate.md

@@ -1,51 +0,0 @@
----
-categories:
-  - Computer Architecture
-  - Electronics
-  - Hardware
-tags: [logic-gates, binary]
----
-
-# NOT gate
-
-This gate corresponds to the negation logical connective.
-
-Negation switches the value of a proposition from `true` to `false`. When we put `~` before `true` it becomes `false` and when we put `~` before `false` it becomes `true` .
-
-The truth-table for negation:
-````
-P			~P
-T			F	
-F			T
-````
-In terms of gates this logic obviously corresponds to a simple on/off switch. 
-
-In terms of pure logic, negation is an unary connective in contrast to binary connectives like conjuction and disjunction. It doesn't operate on two parts it simply switches the truth value of whichever proposition it is applied to. 
-
-How then, can it be expressed in terms of a gate that takes two inputs and returns an output? Well, we can recreate the logic by manipulating a NAND gate. (Demonstrating the point that many logical conditions are expressible purely via NAND gates.)
-
-Although a NAND can take a total of two inputs, it would be controlled by a single switch, such that both inputs would be set to `1 1` or `0 0` when the switch is activated and deactivated. This would remove the `AND` aspect of `NAND` and reduce it to `NOT` .
-
-A NAND gate simulating NOT logic
-
-![Screenshot_2020-08-25_at_15.09.01.png](../../img/Screenshot_2020-08-25_at_15.09.01.png)
-
-Going back to the truth-conditions for NAND, NAND-as-NOT just means that the conditons on lines 1 and 4 obtain:
-
-```
-A    B     C
-_    _     _
-
-0    0     1      1    
-1    0     1      2 
-0    1     1      3 
-1    1     0      4
-```
-
-### Symbol for `NOT` gate
-
-NOT has its own electrical symbol to distinguish it from a NAND:
-
-![Screenshot_2020-08-25_at_15.18.34.png](../../img/Screenshot_2020-08-25_at_15.18.34.png)
-
-Note that as this is an abstraction of the process, there is no need to show two inputs in the representation of the gate. We have a single input and single output reflecting the unary nature of the negation operator.