From 3ddc9f0dffb0ff9de9000be535379540afee9af7 Mon Sep 17 00:00:00 2001 From: thomasabishop Date: Tue, 11 Jul 2023 07:22:40 +0100 Subject: [PATCH] architecture: prose changes Bus entry --- Computer_Architecture/Bus.md | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/Computer_Architecture/Bus.md b/Computer_Architecture/Bus.md index 81c5160..33dd3e8 100644 --- a/Computer_Architecture/Bus.md +++ b/Computer_Architecture/Bus.md @@ -2,18 +2,19 @@ categories: - Computer Architecture - Hardware -tags: [motherboard] +tags: [bus] --- # Bus -A bus is a communication system that transfers data between components inside a computer, or between computers. **A bus can be thought of as a kind of pipeline that allows different components of the computer to communicate with each other.** +A bus is a communication system that transfers data between components inside a computer, or between computers. + +**A bus can be thought of as a kind of pipeline that allows different components of the computer to communicate with each other.** Note that the use of the word "bus" varies somewhat in points of emphasis. A bus can mean: - The physical wires that make up the bus -- The logical communication channel that is established over those wires -- TheBany\_. +- The communication channel that is established over those wires ## Main buses @@ -23,7 +24,7 @@ Note that the use of the word "bus" varies somewhat in points of emphasis. A bus | Internal bus | Connects local devices for example the harddisk to the CPU. | | External bus | Connects peripheral devices such as disks and printers to the [motherboard](/Electronics_and_Hardware/Motherboard.md) | | Expansion bus | Allows expansion boards to access the CPU and memory. | -| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Electronics_and_Hardware/Motherboard.md) devices. | +| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](/Electronics_and_Hardware/Motherboard.md) devices. | | Backside bus | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations | ## Bus standards