From 3d7ec2e08133e4133083903d9503c9a0344c52d1 Mon Sep 17 00:00:00 2001
From: thomasabishop <tactonbishop@gmail.com>
Date: Sat, 20 Apr 2024 12:30:04 +0100
Subject: [PATCH] Autosave: 2024-04-20 12:30:04

---
 .zk/notebook.db | Bin 3244032 -> 3244032 bytes
 zk/Bus.md       |  17 ++++++++---------
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/.zk/notebook.db b/.zk/notebook.db
index bc45b35d0d2e91fd945276f2e4624bc41599e5b6..3ef05791b30762d01bac0d40522a6b48a5f3e0db 100644
GIT binary patch
delta 8398
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diff --git a/zk/Bus.md b/zk/Bus.md
index 7621e15..cc9e688 100644
--- a/zk/Bus.md
+++ b/zk/Bus.md
@@ -18,14 +18,14 @@ can mean:
 
 ## Main buses
 
-| Bus type      | Description                                                                                                                                                                                                                                      |
-| ------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
+| Bus type      | Description                                                                                                                                                                                                        |
+| ------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
 | System bus    | The primary pathway between the CPU and [memory](Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory. |
-| Internal bus  | Connects local devices for example the harddisk to the CPU.                                                                                                                                                                                      |
-| External bus  | Connects peripheral devices such as disks and printers to the [motherboard](Motherboard.md)                                                                                                                            |
-| Expansion bus | Allows expansion boards to access the CPU and memory.                                                                                                                                                                                            |
-| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Motherboard.md) devices.                                                 |
-| Backside bus  | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations                                                                                                                                               |
+| Internal bus  | Connects local devices for example the harddisk to the CPU.                                                                                                                                                        |
+| External bus  | Connects peripheral devices such as disks and printers to the [motherboard](Motherboard.md)                                                                                                                        |
+| Expansion bus | Allows expansion boards to access the CPU and memory.                                                                                                                                                              |
+| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Motherboard.md) devices.                                             |
+| Backside bus  | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations                                                                                                                 |
 
 ## Bus standards
 
@@ -44,8 +44,7 @@ transmit each bit of data simultaneously.
 <img src="../img/parallel-transmission.jpg" width="800px"/>
 
 - Serial buses are cheaper to implement than parallel buses
-- Serial buses operate at greater
-  [latency](Bus.md#latency) than parallel buses
+- Serial buses operate at greater [latency](Bus.md#latency) than parallel buses
 
 ## Latency