diff --git a/.zk/notebook.db b/.zk/notebook.db index bc45b35..3ef0579 100644 Binary files a/.zk/notebook.db and b/.zk/notebook.db differ diff --git a/zk/Bus.md b/zk/Bus.md index 7621e15..cc9e688 100644 --- a/zk/Bus.md +++ b/zk/Bus.md @@ -18,14 +18,14 @@ can mean: ## Main buses -| Bus type | Description | -| ------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | +| Bus type | Description | +| ------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | | System bus | The primary pathway between the CPU and [memory](Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory. | -| Internal bus | Connects local devices for example the harddisk to the CPU. | -| External bus | Connects peripheral devices such as disks and printers to the [motherboard](Motherboard.md) | -| Expansion bus | Allows expansion boards to access the CPU and memory. | -| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Motherboard.md) devices. | -| Backside bus | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations | +| Internal bus | Connects local devices for example the harddisk to the CPU. | +| External bus | Connects peripheral devices such as disks and printers to the [motherboard](Motherboard.md) | +| Expansion bus | Allows expansion boards to access the CPU and memory. | +| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Motherboard.md) devices. | +| Backside bus | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations | ## Bus standards @@ -44,8 +44,7 @@ transmit each bit of data simultaneously. - Serial buses are cheaper to implement than parallel buses -- Serial buses operate at greater - [latency](Bus.md#latency) than parallel buses +- Serial buses operate at greater [latency](Bus.md#latency) than parallel buses ## Latency