diff --git a/Algorithms/Algorithmic_complexity.md b/Algorithms/Algorithmic_complexity.md index fd3ee2c..3766540 100644 --- a/Algorithms/Algorithmic_complexity.md +++ b/Algorithms/Algorithmic_complexity.md @@ -2,7 +2,7 @@ tags: [algorithms] --- -![Screenshot_2021-05-11_at_18.55.23.png](../img/Screenshot_2021-05-11_at_18.55.23.png) +![Screenshot_2021-05-11_at_18.55.23.png](../_img/Screenshot_2021-05-11_at_18.55.23.png) _Summary of the main classes of algorithmic complexity_ ## Distinguish algorithms from programs @@ -65,7 +65,7 @@ If we say that it takes 1ms for two integers to be summed, this gives us the fol | 4 | 4 | | 5 | 5 | -If we plotted this as a graph it is clear that this is equivalent to a linear distribution:![lin.svg](../img/lin.svg) +If we plotted this as a graph it is clear that this is equivalent to a linear distribution:![lin.svg](../_img/lin.svg) Algorithms which display this distribution are therefore called **linear algorithms**. @@ -134,7 +134,7 @@ If the input had length 4, the runtime would be 16 or 4x4. For every execution o This is not a linear algorithm because as n grows the runtime increases as a factor of it. Therefore the runtime is not growing proportional to the size of the input, it is growing proportional to the size of the input squared. Graphically this is represented with a curving lines as follows: -![square.svg](../img/square.svg) +![square.svg](../_img/square.svg) We can clearly see that as n grows, the runtime gets steeper and more pronounced, @@ -176,7 +176,7 @@ For example, with $\log 25$: Back to algorithms: $O(\log n)$ is a really good complexity to have. It is close to O(1) and in between O(1) and O(n). Represented graphically, it starts of with a slight increase in runtime but then quickly levels off: -![Screenshot_2021-05-11_at_18.51.02.png](../img/Screenshot_2021-05-11_at_18.51.02.png) +![Screenshot_2021-05-11_at_18.51.02.png](../_img/Screenshot_2021-05-11_at_18.51.02.png) Many sorting algorithms run in log n time, as does recursion. @@ -227,7 +227,7 @@ When seeking to simplify algorithms to their most general level of complexity, w With this in mind we can break down the `findSum` function like so: -![breakdown.svg](../img/breakdown.svg) +![breakdown.svg](../_img/breakdown.svg) This gives us: diff --git a/Computer_Architecture/Bus.md b/Computer_Architecture/Bus.md index 47001bb..81c5160 100644 --- a/Computer_Architecture/Bus.md +++ b/Computer_Architecture/Bus.md @@ -5,48 +5,37 @@ categories: tags: [motherboard] --- -# - # Bus -A bus is a communication system that transfers data between components inside a computer, or between computers. +A bus is a communication system that transfers data between components inside a computer, or between computers. **A bus can be thought of as a kind of pipeline that allows different components of the computer to communicate with each other.** + +Note that the use of the word "bus" varies somewhat in points of emphasis. A bus can mean: + +- The physical wires that make up the bus +- The logical communication channel that is established over those wires +- TheBany\_. ## Main buses -### System bus - -The primary pathway between the CPU and [memory](/Computer_Architecture/Memory/Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory. - -### Internal bus - -Connects local devices for example the harddisk to the CPU. - -### External bus - -Connects peripheral devices such as disks and printers to the [motherboard](/Electronics_and_Hardware/Motherboard.md) - -### Expansion bus - -Allows expansion boards to access the CPU and memory. - -### Frontside bus - -Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Electronics_and_Hardware/Motherboard.md) devices. - -### Backside bus - -Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations +| Bus type | Description | +| ------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | +| System bus | The primary pathway between the CPU and [memory](/Computer_Architecture/Memory/Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory. | +| Internal bus | Connects local devices for example the harddisk to the CPU. | +| External bus | Connects peripheral devices such as disks and printers to the [motherboard](/Electronics_and_Hardware/Motherboard.md) | +| Expansion bus | Allows expansion boards to access the CPU and memory. | +| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Electronics_and_Hardware/Motherboard.md) devices. | +| Backside bus | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations | ## Bus standards ### Parallel and serial transmission types -There is a distinction between buses that use serial and buses that use parallel transmission. They are distinguished by the way in which data in the form of bits is transferred from one point to another, along the bus. +There is a distinction between buses that use **serial** and buses that use **parallel transmission**. They are distinguished by the way in which the bits are transferred from one point to another, along the bus. Serial Transmission is the type of transmission in which a single communication link is used to transfer the data from an end to another. On other hand Parallel Transmission is the transmission in which multiple parallel links are used that transmit each bit of data simultaneously. - - + + - Serial buses are cheaper to implement than parallel buses - Serial buses operate at greater [latency](/Computer_Architecture/Bus.md#latency) than parallel buses diff --git a/Computer_Architecture/CPU/CPU_architecture.md b/Computer_Architecture/CPU/CPU_architecture.md index 11b9f69..cab81fb 100644 --- a/Computer_Architecture/CPU/CPU_architecture.md +++ b/Computer_Architecture/CPU/CPU_architecture.md @@ -42,7 +42,7 @@ This is the heart of the CPU; all the other components on the CPU chip are appen Below is a schematic of a series of logical circuits within the CPU core: -![74181aluschematic.png](/img/74181aluschematic.png) +![74181aluschematic.png](/_img/74181aluschematic.png) ### Processor cores @@ -74,6 +74,6 @@ Each "cycle" is the execution of a process that commences once the [kernel](/Ope Hertz was the scientist who detected electromagentic waves and more broadly in science, we use Hertz to measure the frequency of electromatic wave cycles in a signal. -![](/img/hertz_wave_freq.gif) +![](/_img/hertz_wave_freq.gif) As the diagram above shows, a cycle is equal to one ascending and one descending crest. The more cycles per time unit, the greater the Hertz. We see the Hz increase as the number of cycles increases over time. diff --git a/Computer_Architecture/CPU/The_Little_Man_computer.md b/Computer_Architecture/CPU/The_Little_Man_computer.md index 02922b8..a17c93e 100644 --- a/Computer_Architecture/CPU/The_Little_Man_computer.md +++ b/Computer_Architecture/CPU/The_Little_Man_computer.md @@ -10,7 +10,7 @@ tags: [CPU, processors] The [Little Man Computer](https://peterhigginson.co.uk/lmc/) is a simplified computer that works on Von Neuman principles. It has all the CPU components we have detailed above. It is programmed in machine code but for simplicity it uses the denary rather than the binary number system. -![LMC_5.gif](/img/LMC_5.gif) +![LMC_5.gif](/_img/LMC_5.gif) On the left is the instruction set. Each number constitutes and execution routine and the `xx` stand for the address in RAM that the execution will work on. diff --git a/Computer_Architecture/Hardware_Description_Language.md b/Computer_Architecture/Hardware_Description_Language.md new file mode 100644 index 0000000..b3cb55a --- /dev/null +++ b/Computer_Architecture/Hardware_Description_Language.md @@ -0,0 +1,84 @@ +--- +categories: + - Computer Architecture + - Hardware +tags: [HDL, nand-to-tetris] +--- + +# Hardware Description Language + +An HDL is a declarative programming language used to describe the behaviour or structure of [digital circuits](/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md). They are used to simulate the circuit and check its response. + +The hardware designer specifies a chip's logic by writing an HDL program which is then rigorously tested. At this stage, a [hardware simulator](/Computer_Architecture/Hardware_simulation.md) takes the HDL program as input and creates a software representation of the chip logic. The designer can instruct the simulator to test the virtual chip on various sets of inputs. This is done to check the chip's functionality but also to benchmark a variety of other parameters such as speed of computation and energy consumption. + +There are many HDLs but the most popular are VHDL ("very high speed integrated-circuit description language") and Verilog. + +## Usage in _NAND to Tetris_ + +We won't use an actual HDL language, instead we will use a simplified toy language called HDL that is simple enough that when it is used with a simulator, we can learn the main facets of chip design. Its syntax is very similar to VHDL. + +## Demonstration of HDL program + +### Boolean function to enact + +We will create an HDL program for an XOR gate that is implemented through the following arrangement of NOT, AND, and OR gates: + +![](/_img/xor-hdl.png) + +### HDL file (`Xor.hdl`): + +Here is our HDL file: + +```vhdl +/* Xor gate + If a!=b out=1 else out=0 +*/ +CHIP Xor { + IN a, b; + OUT out; + PARTS: + Not (in=a, out=nota); + Not (in=b, out=notb); + And (a=a, b=notb, out=w1); + And (a=nota, b=b, out=w2); + Or (a=w1, b=w2, out=out) +} +``` + +#### Interface (`CHIP, IN, OUT`) + +At the top level of the HDL program, the `CHIP` name and `IN`/`OUT` declaration is the _interface_ of the chip. Here we specify our naming convention for the `IN` and `OUT` values which we will refer to in the implementation declaration in `PARTS`. + +#### Implementation (`PARTS`) + +Everything under the `PARTS` section is the chip _implementation_. We can draw on composite gates in the `PARTS` declaration (e.g. `Not`, `And`, `Or`). The convention is to work from left to right when transcribing from a digital circuit diagram + +#### Pins + +In an HDL program we distinguish internal pins along with the standard [input and output pins](/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md). At the level of the interface, we are concerned only with input and output pins (in the example program these are `a`, `b` and `out`). It is at the level of the implementation that internal pins are encountered. In the example these are the connections between, e.g. the AND and NOT gates such as `And (a=a, b-notb, out=w1)`. This means the AND gate is receiving through its `a` pin the input `a` value and through its `b` pin the value of `b` inverted by a NOT. `out` is the value that is computed based on the input pins of `a` and `b`. + +### Test file (`Xor.tst`) + +Along with the HDL file we also create a test file. This runs the chip against the inputs we supply, these will typically be equivalent to the (left-hand) truth-values column in a truth table which is the same as the parameters passed to a [Boolean function](/Logic/Propositional_logic/Boolean_functions.md), for example: + +```vhdl +load Xor.hdl +output-list a, b, out; +set a 0, set b 0, eval, output; +set a 0, set b 1, eval, output; +set a 1, set b 0, eval, output; +set a 1, set b =, eval, output; +``` + +### Output file (`Xor.out`) + +When the test file is run against the HDL file it will generate an output file. This is effectively the result of the unit test. And will take the form of a truth table: + +``` +a | b | out +----------- +0 | 0 | 0 +0 | 1 | 1 +1 | 0 | 1 +1 | 1 | 0 +``` diff --git a/Computer_Architecture/Hardware_abstraction_and_modularity.md b/Computer_Architecture/Hardware_abstraction_and_modularity.md index 33eed68..81fd361 100644 --- a/Computer_Architecture/Hardware_abstraction_and_modularity.md +++ b/Computer_Architecture/Hardware_abstraction_and_modularity.md @@ -2,7 +2,7 @@ categories: - Computer Architecture - Hardware -tags: [abstraction, modules] +tags: [abstraction, modules, nand-to-tetris] --- # Hardware abstraction and modularity @@ -24,4 +24,4 @@ When using a module as a building block you are to focus exclusively on the modu The design of the diagram below emphasises the role of abstraction and modularity in the movement from transistors to chips: -![](/img/hardware-abstraction-hierarchy.png) +![](/_img/hardware-abstraction-hierarchy.png) diff --git a/Computer_Architecture/Hardware_simulation.md b/Computer_Architecture/Hardware_simulation.md new file mode 100644 index 0000000..2d05168 --- /dev/null +++ b/Computer_Architecture/Hardware_simulation.md @@ -0,0 +1,57 @@ +--- +categories: + - Computer Architecture + - Hardware +tags: [HDL, nand-to-tetris] +--- + +# Hardware simulation + +In order to test our [HDL](/Computer_Architecture/Hardware_Description_Language.md) files we load them into the hardware simulator program. We will demonstrate this with the following XOR implementation: + +![](/_img/xor-addition-four.png) + +There are several simulation options: + +- interactive +- script-based (where we load a test script into the simulator along with the HDL file +- comparative (running the HDL program against our intended output specified in the `.cmp` file) + +The use-cases for each mode are based on the complexity of the chip you are evaluating. For a small chip, interactive and script-based testing would be sufficient but for much larger components like an ALU a comparative approach would be more manageable and efficient. + +## Interactive + +The image below shows a basic interactive usage of the simulator. We have uploaded the `Xor.hdl` file into the simulator and changed the input pins to `a=1, b=0` and clicked the calculator icon (representing "evaluation"). This then shows the output and internal pin values for these inputs. + + + +## Script-based + +This time we have clicked the script icon to load `Xor.tst`. This loads the test script into the main GUI panel on the left. We can step through each line of the test file and we will see the pin values update in accordance with the test. + +When this is run it automatically generates an output file in the source directory at `Xor.out`. This can be viewed within the simulator via the 'View' drop down. + +![](/_img/hd-sim-test.png) + +## Comparison-based + +With a comparison-based approach to chip testing we run a comparison against the `.out` file that the simulator generates when running the HDL program against a `.cmp` comparison file that we provide. Both are simply truth-tables. For XOR if the program matched the comparison specification both `Xor.out` and `Xor.cmp` would look like the following: + +``` +a | b | out +----------- +0 | 0 | 0 +0 | 1 | 1 +1 | 0 | 1 +1 | 1 | 0 +``` + +You don't have to do anything to apply the comparison since the compare file will already be loaded as part of the test file's set up: + +```vhdl +load Xor.hdl +output file Xor.out +compare-to Xor.cmp +output-list a, b, out; +set ... +``` diff --git a/Computer_Architecture/Memory/Memory.md b/Computer_Architecture/Memory/Memory.md index 900b44a..1fc13f4 100644 --- a/Computer_Architecture/Memory/Memory.md +++ b/Computer_Architecture/Memory/Memory.md @@ -43,7 +43,7 @@ The table below details the relative speeds of the different types of memory and The diagram below compares the different forms of memory within a computing device in terms of speed, monetary cost and capacity: -![](/img/Memory-Hierarchy.jpg) +![](/_img/Memory-Hierarchy.jpg) ## References diff --git a/Computer_Architecture/Memory/Role_of_memory_in_computation.md b/Computer_Architecture/Memory/Role_of_memory_in_computation.md index 5dc7388..51bbd60 100644 --- a/Computer_Architecture/Memory/Role_of_memory_in_computation.md +++ b/Computer_Architecture/Memory/Role_of_memory_in_computation.md @@ -15,7 +15,7 @@ The following steps outline the way in which memory interacts with the processor > This is a simplified account; it is not the case that only single requests are passed back and forth. This would be inefficient and time-wasting. The kernel sends to the CPU not just the first instruction in the requested file but also a number of instructions that immediately follow it. -![](/img/memory-flow.svg) +![](/_img/memory-flow.svg) Every part of the above process - the journey accross the bus, the lookup in the controller, the operations on the DRAM, the journey back accross the bus - takes muliple CPU clock cycles. diff --git a/Data_Structures/Queue.md b/Data_Structures/Queue.md index c8e1cf0..3df2f75 100644 --- a/Data_Structures/Queue.md +++ b/Data_Structures/Queue.md @@ -8,7 +8,7 @@ tags: _Visualization of the queue data structure_ -![queue.svg](../img/queue.svg) +![queue.svg](../_img/queue.svg) ## A queue is a sequential data structure and most similar to a stack diff --git a/Data_Structures/Recursion.md b/Data_Structures/Recursion.md index ee34ce4..6cdac93 100644 --- a/Data_Structures/Recursion.md +++ b/Data_Structures/Recursion.md @@ -13,7 +13,7 @@ More generally recursion means when a thing is defined in terms of itself. There ## Schema The general structure of a recursive function is as follows: -![javascript-recursion.png](../img/javascript-recursion.png) +![javascript-recursion.png](../_img/javascript-recursion.png) ## Why use recursive functions? @@ -111,4 +111,4 @@ if (num > 0) { } ``` -![javascript-factorial 1.png](../img/javascript-factorial%201.png) +![javascript-factorial 1.png](../_img/javascript-factorial%201.png) diff --git a/Data_Structures/Stacks.md b/Data_Structures/Stacks.md index 1805469..82169ac 100644 --- a/Data_Structures/Stacks.md +++ b/Data_Structures/Stacks.md @@ -6,10 +6,10 @@ tags: --- _A stack visualised vertically_ -![stack2.svg](../img/stack2.svg) +![stack2.svg](../_img/stack2.svg) _A stack visualised horizontally_ -![stack1.svg](../img/stack1.svg) +![stack1.svg](../_img/stack1.svg) ## A stack is a linear data structure that observes LIFO diff --git a/Databases/GraphQL/Apollo/Apollo_Server.md b/Databases/GraphQL/Apollo/Apollo_Server.md index 84f130c..8bb1ea1 100644 --- a/Databases/GraphQL/Apollo/Apollo_Server.md +++ b/Databases/GraphQL/Apollo/Apollo_Server.md @@ -72,7 +72,7 @@ server.listen().then(() => { When we access the local URL we are able to access the Apollo server using the Explorer GUI. This automatically loads our schema and is basically a more fancy version of GraphiQL: -![](/img/apollo-explorer.png) +![](/_img/apollo-explorer.png) It makes it easy to read descriptions of the dataypes and to construct queries by clicking to insert fields. diff --git a/Databases/GraphQL/Journey_of_GraphQL_query.md b/Databases/GraphQL/Journey_of_GraphQL_query.md index 64c1122..2ddd1a3 100644 --- a/Databases/GraphQL/Journey_of_GraphQL_query.md +++ b/Databases/GraphQL/Journey_of_GraphQL_query.md @@ -6,4 +6,4 @@ tags: [graphql] # The journey of a GraphQL query -![](/img/graphql-journey-two.svg) +![](/_img/graphql-journey-two.svg) diff --git a/Databases/GraphQL/Key_characteristics_of_GraphQL.md b/Databases/GraphQL/Key_characteristics_of_GraphQL.md index 670c688..838a780 100644 --- a/Databases/GraphQL/Key_characteristics_of_GraphQL.md +++ b/Databases/GraphQL/Key_characteristics_of_GraphQL.md @@ -26,7 +26,7 @@ From the point of view of the backend, GraphQL is a **runtime** that provides a Client requests are sent over HTTPS and the data is typically returned in the form of JSON: -![](/img/graphql-architecture.png) +![](/_img/graphql-architecture.png) ## Implementation overview @@ -83,15 +83,15 @@ With a REST API if you require multiple resources you have to make multiple requ The REST scenario: -![](/img/REST_request-load.png) +![](/_img/REST_request-load.png) The GraphQL scenario: -![](/img/graphQL_request_load.png) +![](/_img/graphQL_request_load.png) ### Abstraction of multiple services -![](/img/graphql_multiple_resources.png) +![](/_img/graphql_multiple_resources.png) ### Stops overfetching diff --git a/Databases/MongoDB/Adding_documents_to_a_collection.md b/Databases/MongoDB/Adding_documents_to_a_collection.md index 5f104b1..d560cc9 100644 --- a/Databases/MongoDB/Adding_documents_to_a_collection.md +++ b/Databases/MongoDB/Adding_documents_to_a_collection.md @@ -44,4 +44,4 @@ When we run this, we call the `save` method on the Mongoose schema. We will then This will also be reflected in Compass: -![](/img/mongo-doc-added.png) +![](/_img/mongo-doc-added.png) diff --git a/Databases/MongoDB/Create_database.md b/Databases/MongoDB/Create_database.md index 1c6cc92..0cb16ff 100644 --- a/Databases/MongoDB/Create_database.md +++ b/Databases/MongoDB/Create_database.md @@ -25,4 +25,4 @@ This will run continuously in the terminal and should say somewhere that it is w _Compass_ is a graphical interface for viewing and interacting with the data in your Mongo database. It will automatically load to the default Mongo port: `27017`. -![](/img/mongo-compass.png) +![](/_img/mongo-compass.png) diff --git a/Databases/MongoDB/Creating_a_schema_and_model.md b/Databases/MongoDB/Creating_a_schema_and_model.md index ad94983..d45be46 100644 --- a/Databases/MongoDB/Creating_a_schema_and_model.md +++ b/Databases/MongoDB/Creating_a_schema_and_model.md @@ -61,10 +61,10 @@ const course = new Course({ }); ``` -![](/img/mongoose-hierarchy.svg) +![](/_img/mongoose-hierarchy.svg) ## Outcome Having created a database, connected to it with Mongoose, and created a model we will see our collection reflected in Compass: -![](img/../../../img/mongo-collection.png) +![](img/../../../_img/mongo-collection.png) diff --git a/Databases/MongoDB/Introduction.md b/Databases/MongoDB/Introduction.md index f701ea4..2f693a7 100644 --- a/Databases/MongoDB/Introduction.md +++ b/Databases/MongoDB/Introduction.md @@ -16,4 +16,4 @@ Although Mongo is not a relational database it has a structure that we can under A document is a container comprising key-value pairs in the manner of an object. -![](/img/mongo-db-structure.svg) +![](/_img/mongo-db-structure.svg) diff --git a/Databases/Relational_Databases/Relational_database_architecture.md b/Databases/Relational_Databases/Relational_database_architecture.md index 7743cdb..8a21548 100644 --- a/Databases/Relational_Databases/Relational_database_architecture.md +++ b/Databases/Relational_Databases/Relational_database_architecture.md @@ -8,7 +8,7 @@ tags: [relational-database] Tables, fields and records are the basic building blocks of databases -![](/img/FL-Databases-1.5_terminology.gif) +![](/_img/FL-Databases-1.5_terminology.gif) ## Table diff --git a/Databases/SQL/Joins_in_SQL.md b/Databases/SQL/Joins_in_SQL.md index 3cdeb83..16db1fd 100644 --- a/Databases/SQL/Joins_in_SQL.md +++ b/Databases/SQL/Joins_in_SQL.md @@ -76,7 +76,7 @@ ON model.model_id = sales.model_id; -- Specify the match criteria We can represent the logical relationship that obtains between the `sales` and `model` tables as follows: -![](/img/sql-inner-join.png) +![](/_img/sql-inner-join.png) ## Outer joins @@ -118,7 +118,7 @@ In the context of our dataset, in the _sales_ database we have a row where there The logical relationship sustained between `sales` and `model` by a left inner join is represented in the following diagram: -![](/img/sql-left-outer-join.png) +![](/_img/sql-left-outer-join.png) #### Implementation @@ -153,7 +153,7 @@ In the context of our dataset, in the _model_ database we have a row where there The logical relationship sustained between `sales` and `model` by a right inner join is represented in the following diagram: -![](/img/sql-right-outer-join.png) +![](/_img/sql-right-outer-join.png) #### Implementation @@ -191,7 +191,7 @@ In the context of our dataset it would result in the following table being gener Represented by the following diagram: -![](/img/sql-full-outer-join.png) +![](/_img/sql-full-outer-join.png) #### Implementation diff --git a/Electronics_and_Hardware/Analogue_and_digital.md b/Electronics_and_Hardware/Analogue_and_digital.md index 41fec29..27f18d2 100644 --- a/Electronics_and_Hardware/Analogue_and_digital.md +++ b/Electronics_and_Hardware/Analogue_and_digital.md @@ -9,7 +9,7 @@ tags: [analogue, digital] Analogue and digital are paradigms for recording information, specifically information about an object or state that obtains in the world. -![](/img/analog-digital.svg) +![](/_img/analog-digital.svg) ## Analogue diff --git a/Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md b/Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md index 6ab3a81..bdf3833 100644 --- a/Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md +++ b/Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md @@ -24,7 +24,7 @@ Cells and batteries can be connected to each other in electrical ciruits to incr The table below summarises the relative differences: -![](/img/cell-comparison.svg) +![](/_img/cell-comparison.svg) ### Series connections @@ -43,11 +43,11 @@ Thus series connections increase voltage but keep current constant. _Series battery connection:_ -![](/img/series-battery-diagram.svg) +![](/_img/series-battery-diagram.svg) _Can be represented in a circuit diagram in one of the following two ways: as a series of cells or as a single battery:_ -![](/img/series-battcircuit.svg) +![](/_img/series-battcircuit.svg) In the case of **series opposing**, negative terminals are connected to each other and positive terminals are connected to each other in a series. This doesn't have many applications. @@ -67,11 +67,11 @@ $$ _Parallel battery connection:_ -![](/img/parallel-battery-diagram.svg) +![](/_img/parallel-battery-diagram.svg) _Parallel battery circuit diagram:_ -![](/img/circ-batt-final.svg) +![](/_img/circ-batt-final.svg) ### Series-parrallel diff --git a/Electronics_and_Hardware/Analogue_circuits/Circuits.md b/Electronics_and_Hardware/Analogue_circuits/Circuits.md index d9b251b..2a53a79 100644 --- a/Electronics_and_Hardware/Analogue_circuits/Circuits.md +++ b/Electronics_and_Hardware/Analogue_circuits/Circuits.md @@ -10,7 +10,7 @@ An electrical circuit is a set of electrical components connected in such a way Below is a basic circuit representing a 9-volt [battery](/Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md#cells-and-batteries) with a 10,000$\Omega$ [resistor](/Electronics_and_Hardware/Analogue_circuits/Resistance.md) attached accross its terminals. Through the application of [Ohm's Law](/Electronics_and_Hardware/Physics_of_electricity/Ohms_Law.md) we can determine that the maximum current will be 0.9 miliamps. -![](/img/basic-circuit.png) +![](/_img/basic-circuit.png) ## Open and short circuits @@ -24,4 +24,4 @@ Sometimes circuits can be represented in a vertical manner rather than in an act The circuit below is functionally identical to the previous circuit but represented vertically: -![](/img/vertical-circuit.png) +![](/_img/vertical-circuit.png) diff --git a/Electronics_and_Hardware/Analogue_circuits/Current.md b/Electronics_and_Hardware/Analogue_circuits/Current.md index 5452c1b..4547806 100644 --- a/Electronics_and_Hardware/Analogue_circuits/Current.md +++ b/Electronics_and_Hardware/Analogue_circuits/Current.md @@ -22,7 +22,7 @@ When the terminals are connected to each other via a conductor (e.g. copper wire _The diagram below illustrates the flow of current where the circles are electrons knocking into each other and passing current:_ -![](/img/charge-cylinder.svg) +![](/_img/charge-cylinder.svg) > Electrons travel very slowly through a conductor. This is in contrast to their intrinsic motion which of course equal to the speed of light (186, 000 miles per second). diff --git a/Electronics_and_Hardware/Analogue_circuits/Ground.md b/Electronics_and_Hardware/Analogue_circuits/Ground.md index 7db5777..aa8954b 100644 --- a/Electronics_and_Hardware/Analogue_circuits/Ground.md +++ b/Electronics_and_Hardware/Analogue_circuits/Ground.md @@ -17,4 +17,4 @@ In circuit diagrams with simple DC current, ground is taken to be the negative t The symbol for ground in circuit diagrams: - + diff --git a/Electronics_and_Hardware/Analogue_circuits/LEDs.md b/Electronics_and_Hardware/Analogue_circuits/LEDs.md index fba6a1e..6027624 100644 --- a/Electronics_and_Hardware/Analogue_circuits/LEDs.md +++ b/Electronics_and_Hardware/Analogue_circuits/LEDs.md @@ -8,10 +8,10 @@ tags: [electricity, electrical-circuits] LED' stands for **Light Emitting Diode**, a [circuit]() component that emits light. The symbol for an LED is displayed below: -![](/img/diode-led.png) +![](/_img/diode-led.png) A **diode** is a special kind of component that only permits current to flow through it in one direction. To achieve this it has very low resistance in one direction to allow current flow and high resistance in the other direction to impede current flow. This feature of diodes is clearly represented in the generic diode circuit symbol: -![](/img/diode.png) +![](/_img/diode.png) An LED diode lights up when the right amount of current flows through it. A standard LED has a maximum current of 20mA. An appropriate [resistor](/Electronics_and_Hardware/Analogue_circuits/Resistance.md#resistors) must therefore be added to the circuit to ensure the current doesn't exeedd this amount. diff --git a/Electronics_and_Hardware/Analogue_circuits/Voltage.md b/Electronics_and_Hardware/Analogue_circuits/Voltage.md index 44f50da..2abd863 100644 --- a/Electronics_and_Hardware/Analogue_circuits/Voltage.md +++ b/Electronics_and_Hardware/Analogue_circuits/Voltage.md @@ -60,7 +60,7 @@ The relationship between voltage rise and voltage drop is expressed in Kirchoff' The application of the Law is illustrated in the following diagram: -![](/img/voltage-drop.png) +![](/_img/voltage-drop.png) The explanation for the voltage drop at the positions $V^{A}$ and $V^{D}$ are obvious enough: they are at the beginning and end of the loop so are equal to the maximal voltage rise and minimal voltage drop, respectively. diff --git a/Electronics_and_Hardware/Binary/Binary_arithmetic.md b/Electronics_and_Hardware/Binary/Binary_arithmetic.md index 670413e..6ed6fa1 100644 --- a/Electronics_and_Hardware/Binary/Binary_arithmetic.md +++ b/Electronics_and_Hardware/Binary/Binary_arithmetic.md @@ -33,7 +33,7 @@ Let's break down each column from the right: ### More examples to practise with -![](../img/../../img/Pasted_image_20220319174839.png) +![](../_img/../../_img/Pasted_image_20220319174839.png) ## Binary multiplication @@ -64,10 +64,10 @@ When we multiply binary numbers in columns we multiply each of the top numbers b An important difference is that when we move along the bottom row from the $2^0$, to $2^2$, to $2^4$ etc we must put a zero in the preceding column as a place holder. The sequence is shown below: -![](/img/multiplication_01.gif) +![](/_img/multiplication_01.gif) -![](/img/multiplication_02.gif) +![](/_img/multiplication_02.gif) -![](/img/multiplication_03.gif) +![](/_img/multiplication_03.gif) -![](/img/multiplication_04.gif) +![](/_img/multiplication_04.gif) diff --git a/Electronics_and_Hardware/Binary/Binary_colour_encoding.md b/Electronics_and_Hardware/Binary/Binary_colour_encoding.md index 50c5077..6f76b56 100644 --- a/Electronics_and_Hardware/Binary/Binary_colour_encoding.md +++ b/Electronics_and_Hardware/Binary/Binary_colour_encoding.md @@ -16,7 +16,7 @@ We can start with a limited palette: greyscale. Here there is black and white an In decimal, 0 is equal to black (zero light intensity) and 255 is equal to white (full light intensity). Some examples of this (including binary and hex representations are below): -![](/img/greyscale-encoding.svg) +![](/_img/greyscale-encoding.svg) ### Colour encoding @@ -28,12 +28,12 @@ Some examples below Red is represented in RGB with all 8 red bits to set to 1 and the remaining 16 bits for the other two colours set to 0. -![](/img/red-encoding.svg) +![](/_img/red-encoding.svg) #### Yellow Yellow is represented in RGB with both red and blue set to 1 and the remaining 8 green bits set to ): -![](/img/yellow-encoding.svg) +![](/_img/yellow-encoding.svg) ## Binary encoding of images diff --git a/Electronics_and_Hardware/Binary/Binary_number_system.md b/Electronics_and_Hardware/Binary/Binary_number_system.md index 94b4856..d55d53d 100644 --- a/Electronics_and_Hardware/Binary/Binary_number_system.md +++ b/Electronics_and_Hardware/Binary/Binary_number_system.md @@ -87,11 +87,11 @@ If we have before us the binary place values ($1, 2, 4, 8$). We know that 6 is e More clearly: -![](../../img/Pasted_image_20220319135558.png) +![](../../_img/Pasted_image_20220319135558.png) And for comparison: -![](../../img/Pasted_image_20220319135805.png) +![](../../_img/Pasted_image_20220319135805.png) Or we can express the binary as: @@ -105,4 +105,4 @@ $$ 2^1 + 2^2 $$ Let's convert 23 into binary: -![](../../img/Pasted_image_20220319135823.png) +![](../../_img/Pasted_image_20220319135823.png) diff --git a/Electronics_and_Hardware/Binary/Hexadecimal_number_system.md b/Electronics_and_Hardware/Binary/Hexadecimal_number_system.md index f22d13a..8fae116 100644 --- a/Electronics_and_Hardware/Binary/Hexadecimal_number_system.md +++ b/Electronics_and_Hardware/Binary/Hexadecimal_number_system.md @@ -103,6 +103,6 @@ $$ = 15 $$ -![](/img/hexadecimal-to-bytes.svg) +![](/_img/hexadecimal-to-bytes.svg) > Every four bits (or half byte) in binary corresponds to one symbol in hexadecimal. Therefore **a byte can be easily represented with two hexadecimal symbols, a 16-bit number can be represented with four hex symbols, a 32-bit number can represented with eight hex symbols and so on.** diff --git a/Electronics_and_Hardware/Binary/Signed_and_unsigned_numbers.md b/Electronics_and_Hardware/Binary/Signed_and_unsigned_numbers.md index 9e7dcea..f83579d 100644 --- a/Electronics_and_Hardware/Binary/Signed_and_unsigned_numbers.md +++ b/Electronics_and_Hardware/Binary/Signed_and_unsigned_numbers.md @@ -19,11 +19,11 @@ For example the two's complement of $0101$ (binary 5) is $1011$. There is a simp 1. Take the unsigned number, and flip the bits. In other words: invert the values, so $0$ becomes $1$ and $1$ becomes $0$. 2. Add one -![](/img/unsigned-to-signed.png) +![](/_img/unsigned-to-signed.png) To translate a signed number to an unsigned number you flip them back and still add one: -![](/img/signed-to-unsigned.png) +![](/_img/signed-to-unsigned.png) ### Advantages @@ -66,7 +66,7 @@ Thus for a 4-bit number: Then if we add the decimal equivalents of the place value together, we get our signed number. So in the case of $-3$: -![](/img/signed-conversion.png) +![](/_img/signed-conversion.png) ## Considerations diff --git a/Electronics_and_Hardware/Binary/Why_computers_use_binary.md b/Electronics_and_Hardware/Binary/Why_computers_use_binary.md index 2dcbcaf..5bddfa4 100644 --- a/Electronics_and_Hardware/Binary/Why_computers_use_binary.md +++ b/Electronics_and_Hardware/Binary/Why_computers_use_binary.md @@ -13,13 +13,13 @@ tags: [binary, bits] The reason is straight forward: it is the simplest way on the level of pure engineering of representing numerical and logical values; both of which are the basic foundations of programming. An electronic circuit or transistor only needs to represent two states: on (1) and off (0) which corresponds to the switch on an electrical circuit. A single circuit representing the binary values of 1 and 0: -![multi_on_off 1.gif](../../img/multi_on_off.gif) +![multi_on_off 1.gif](../../_img/multi_on_off.gif) It would be much more complicated to have to represent ten different states under the decimal number system, although denary computers do exist. If we want more digits, we just need to add in more circuits, and we can represent as large a binary number as we need. We just need one switch for every digit we want to represent. The switches used in modern computers are so cheap and so small that billions can be fitted on a single circuit board. -![multiple_circuits.gif](../../img/multiple_circuits.gif) +![multiple_circuits.gif](../../_img/multiple_circuits.gif) When we use the term 'switch' we actually mean the transistor components of a circuit. We don't need to know the physical details at this level but we can say that a transistor turns a current on and off. They can also be used to amplify the current. diff --git a/Electronics_and_Hardware/Digital_circuits/Clock_signals.md b/Electronics_and_Hardware/Digital_circuits/Clock_signals.md index fa3758f..54320c2 100644 --- a/Electronics_and_Hardware/Digital_circuits/Clock_signals.md +++ b/Electronics_and_Hardware/Digital_circuits/Clock_signals.md @@ -10,28 +10,18 @@ tags: [binary, memory, clock, electromagnetism] In the examples of digital circuits so far (i.e [adders](/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md) and [latches](/Electronics_and_Hardware/Digital_circuits/Latches.md)) everything happens in a single instant or over several repeated instances. This is because of how simple the circuits are. In the case of latches only a single bit is updated. And even with rippled adders they are just a series of 1-bit updaters in a chain. -With more complex circuits that use multiple memory devices which store a series of bits at once, we need a way to ensure that the bits are set at the same time. - -We synchronize multiple circuit components with a **clock signal**. - -A clock signal alternates its voltage level from high to low on a regular cadence where it is high half the time and low the rest of the time. This gives the wave form a squared appearence. - +With more complex circuits that use multiple memory devices which store a series of bits at once, we need a way to ensure that the bits are set at theB A single iteration of the volatage rising and falling is a **pulse**. A complete oscillation from low to high and back to low is a **cycle**. As with all [electromagnetic](/Electronics_and_Hardware/Physics_of_electricity/Electromagnetism.md) signals we measure the frequency of the wave in Hertz: cylcles per second. We also further distinguish the rising and falling edge of a pulse. Rising represents the signal passing from ground to its maximum voltage and falling is the reverse (the electrons moving from the voltage source to ground). The diagram below shows a pulse cycle of 2Hz. -![](/img/clock_pulses.png) +![](/_img/clock_pulses.png) ## Linking components to the clock - All components that need to be synchronised are connected to the clock - State changes in the component occur only when a clock pulse occurs -- Clock-driven components will typically trigger their state c| J | K | Clock | Q state | Operation | -|--- |--- |------- |--------------------------- |----------- | -| 0 | 0 | Pulse | Maintain previous value | Hold | -| 0 | 1 | Pulse | 0 | Reset | -| 1 | 0 | Pulse | 1 | Set | -| 1 | 1 | Pulse | Inverse of previous value | Toggle |hanges on either the rising edge or the falling edge of the pulse. +- | Clock-driven components will typically trigger their state changes on either the rising edge or the falling edge of the pulse. | - Components that trigger state changes on the rising pulse are **positive edge-triggered** - Components that trigger state changes on the falling pulse are **negative edge-triggered** diff --git a/Electronics_and_Hardware/Digital_circuits/Creating_memory_with_NAND.md b/Electronics_and_Hardware/Digital_circuits/Creating_memory_with_NAND.md index 59faaba..c6d9670 100644 --- a/Electronics_and_Hardware/Digital_circuits/Creating_memory_with_NAND.md +++ b/Electronics_and_Hardware/Digital_circuits/Creating_memory_with_NAND.md @@ -11,7 +11,7 @@ tags: [logic-gates, binary, memory] The [logic circuit](/Electronics_and_Hardware/Digital_circuits/Digital_circuits.md) below demonstrates how memory can be created using [NAND](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md#nand-gate) gates. A single bit is stored in memory. -![](/img/nand_latch_logic_circuit.png) +![](/_img/nand_latch_logic_circuit.png) Interactive version of circuit: @@ -35,7 +35,7 @@ Interactive version of circuit: > Upshot: With **S** `ON`, output is the same as input -![](/img/nand-mem-first.gif) +![](/_img/nand-mem-first.gif) ### Second state: both S and I `ON` @@ -48,7 +48,7 @@ Interactive version of circuit: > Upshot: With **S** on, the output is again the same as the input -![](/img/nand-mem-second.gif) +![](/_img/nand-mem-second.gif) > So far we have seen that when **S** is `ON` you can change **I** on and off and **O** will change with it. @@ -60,4 +60,4 @@ The specific reason for this is that, if **S** is `OFF`, both **A** and **B** ar This is illustrated in the diagram below. The space occupied by **A** and **B** remains on (note it is illuminated) regardless of the state of **I**. -![](/img/nand-mem-demonstrated.gif) +![](/_img/nand-mem-demonstrated.gif) diff --git a/Electronics_and_Hardware/Digital_circuits/Flip_flops.md b/Electronics_and_Hardware/Digital_circuits/Flip_flops.md index 260cc12..02d053a 100644 --- a/Electronics_and_Hardware/Digital_circuits/Flip_flops.md +++ b/Electronics_and_Hardware/Digital_circuits/Flip_flops.md @@ -28,7 +28,7 @@ The possible state changes for the JK Flip-Flop are detailed below: A JK Flip-Flop can execute on either the positive or negative pulse. Below are the diagrams for a rising and falling pulse respectively: -![](/img/jk-flip-flops.png) +![](/_img/jk-flip-flops.png) @@ -43,7 +43,7 @@ Thus the state table for the T Flip-Flop is: | 0 | Pulse | Maintain previous value | Hold | | 0 | Pulse | Inverse of previous value | Toggle | -![](/img/t-flip-flops.png) +![](/_img/t-flip-flops.png) diff --git a/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md b/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md index 003a210..17c90ee 100644 --- a/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md +++ b/Electronics_and_Hardware/Digital_circuits/Four_bit_adder.md @@ -22,7 +22,7 @@ We will achieve this by using three full adders and one half adder, moving from Let's walk through the process: -![](/img/four-bit-adder.png) +![](/_img/four-bit-adder.png) 1. HA receives the bits $0$ and $1$ as inputs. It outputs $1$ as the sum bit and $0$ as the carry-out. 2. FA1 receives $0$ as the carry-in bit plus $1$ and $1$ as its input. This means it has the following calculation to execute: $1 + 1 + 0$. This gives $0$ as the sum bit and $1$ as the carry-out bit. diff --git a/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md b/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md index 1a1dd67..80e7670 100644 --- a/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md +++ b/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md @@ -50,7 +50,7 @@ The half adder receives two bits (A and B) which are to be added together. It ou The diagram below shows the circuit representation of a half-adder and an example calculation. This calculation matches the ones column of the earlier binary addition example: $0011 + 0010$. -![](/img/half-adder-new.png) +![](/_img/half-adder-new.png) ### Implementation with logic gates @@ -88,7 +88,7 @@ And the carry-out bit replicates the truth conditions of [AND](/Electronics_and_ It is therefore possible to implement a half-adder with just these two logic gates: -![](/img/half-adder-gates-three.png) +![](/_img/half-adder-gates-three.png) The digital circuit above has the same inputs and outputs as the half adder diagram above. @@ -104,7 +104,7 @@ The full adder takes in three inputs and has two outputs. It is identical to the | ---------------------------- | ----------------------------- | ------------------------ | ---------------------- | ---------------------------- | | The first number to be added | The second number to be added | The incoming carried bit | The sum bit (A+B+C_in) | The carry-out bit (A+B+C_in) | -![](/img/full-adder-new.png) +![](/_img/full-adder-new.png) The diagram above is equivalent to the calculation taking place in the fours column. It has received a carry from the twos column ($1 + 1$ results in $1$ as a carry) and then adds this together with its own inputs ($0$ and $0$). diff --git a/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md b/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md index 80f844e..4c6e7c2 100644 --- a/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md +++ b/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md @@ -10,11 +10,13 @@ tags: [logic-gates] An integrated circuit (IC) is a single unit that comprises several logic gates designed for the easy construction of [digital circuits](/Electronics_and_Hardware/Digital_circuits/Digital_circuits.md). The terms "integrated circuit" and "chip" are often used interchangeably. -An IC puts the gates on a single piece of silicon that has electrical contact points called pins. The type we will look at are called **dual in-line packages** (DIPs). They are rectangular wth two parallel rows of pins. The pins make it easy to connect DIPs to a breadboard. +An IC puts the gates on a single piece of silicon that has electrical contact points called pins. There are two types of pins on an IC: input pins and output pins. Input pins are used to receive signals from other components in the circuit, while output pins are used to send signals to other components. The function of a pin is determined by the connection it has to the rest of the circuit and the type of signal it is intended to transmit or receive. + +The type we will look at are called **dual in-line packages** (DIPs). They are rectangular wth two parallel rows of pins. The pins make it easy to connect DIPs to a breadboard. _An integrated circuit and its use on a breadboard:_ - - + + // TODO: Add diagrams of different IC gate types diff --git a/Electronics_and_Hardware/Digital_circuits/Latches.md b/Electronics_and_Hardware/Digital_circuits/Latches.md index d77f841..ef68754 100644 --- a/Electronics_and_Hardware/Digital_circuits/Latches.md +++ b/Electronics_and_Hardware/Digital_circuits/Latches.md @@ -27,12 +27,9 @@ The SR Latch goes through the following state changes: This is represented more clearly in the table below: -| S | R | Q | Operation | -| --- | --- | ----------------------- | ------------- | -| 0 | 0 | Maintain previous value | Hold | -| 0 | 1 | 0 | Reset | -| 1 | 0 | 1 | Set | -| 1 | 1 | X | Invalid, null | +| S | R | Q | Operation | +| --- | --- | ----------------------- | --------- | +| 1 | 1 | X | Invalid, null | The most succinct account of a latch: @@ -40,7 +37,7 @@ The most succinct account of a latch: _The representation of an SR Latch in a digital circuit diagram_: -![](/img/sr_latch_diagram.png) +![](/_img/sr_latch_diagram.png) ## Creating a latch circuit @@ -50,7 +47,7 @@ The two gates are in a **cross-coupled configuration**. This basically means tha The circuit is created as follows: -![](/img/sr_latch_logic_circuit.png) +![](/_img/sr_latch_logic_circuit.png) Interactive version: diff --git a/Electronics_and_Hardware/Digital_circuits/Logic_gates.md b/Electronics_and_Hardware/Digital_circuits/Logic_gates.md index f88db6a..c5f2a11 100644 --- a/Electronics_and_Hardware/Digital_circuits/Logic_gates.md +++ b/Electronics_and_Hardware/Digital_circuits/Logic_gates.md @@ -8,10 +8,33 @@ tags: [logic-gates, binary] # Logic gates -> [A logic gate consists in] three connections where there may or may not be some electricity. Two of those connections are places where electricity may be put into the device, and the third connection is a place where electricity may come out of the device. (Scott, 2009 p.21) +> [A logic gate consists in] three connections where there may or may not be some electricity. Two of those connections are places where electricity may be put into the device, and the third connection is a place where electricity may come out of the device. -Logic gates are the basic building blocks of digital computing. **A logic gate is an electrical circuit that has one or more than one input and only one output.** The input controls the output and the logic determining which types of input (on/off) lead to specific outputs (on/off) is identical to the truth-conditions of the [Boolean connectives](/Logic/Truth-functional_connectives.md) specifiable in terms of [truth-tables](/Logic/Truth-tables.md). -Physically, what 'travels through' the gates is electrical current and what constitutes the 'gate' is a [transistor](/Electronics_and_Hardware/Digital_circuits/Transistors.md) responding to the current. At the next level of abstraction it is bits that go into the gate and bits which come out: binary information that may be either 1 or 0. +[J.C. Scott. 2009. **But How Do It Know? The Basics of Computers for Everyone**, 21] + +Logic gates are the basic building blocks of digital computing. **A logic gate is an electrical circuit that has one or more than one input and only one output.** The input and output points of the gate are [pins](/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md) The input controls the output and the logic determining which types of input (on/off) lead to specific outputs (on/off) is isomorphic with the truth-conditions of the [Boolean connectives](/Logic/Truth-functional_connectives.md) specifiable in terms of [truth tables](/Logic/Truth-tables.md). + +Physically, what 'travels through' the gates is electrical current and what constitutes the 'gate' is a [transistor](/Electronics_and_Hardware/Digital_circuits/Transistors.md) responding to the current. Going up a level of abstraction, the current/ charge is identified with a [bit](/Electronics_and_Hardware/Binary/Binary_units_of_measurement.md#binary-units-of-measurement). It is bits that go into the gate and bits which come out: binary information that may be either 1 or 0. + +## Elementary and composite gates + +We distinguish elementary from composite logic gates. An elementary gate is a single gate embodying a single logical connective. It cannot be reduced any lower as a logical abstraction. A composite gate is a gate made up of more than one elementary gate and/or other composite gates. + +An example of a composite gate would be a three-way AND. An AND with three inputs rather than the standard two that furnish the elementary AND gate. This gate would output 1 when all three gates have the value 1 and 0 otherwise. [Adders](/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md) and [latches](/Electronics_and_Hardware/Digital_circuits/Latches.md) whilst being [integrated circuits](/Electronics_and_Hardware/Digital_circuits/Integrated_circuits.md) are also, technically speaking, composite gates. + +## Gate interface / gate implementation + +The gate _interface_ is an abstraction that the enables the user to think of the gate simply in terms of inputs and outputs, without being concerned with the technical details of how this is achieved. How it is achieved is the gate _implementation_. + +We can demonstrate this with the earlier example of a three-way AND. The diagram below represents the gate as an interface: + +// TODO: Interface diagram + +Whereas this diagram presents the implementation of the gate: it shows the specific combination of gates which creates the enables the behaviour represented in the interface diagram. + +// TODO: Implementation diagram + +> Importantly, a single interface may be implemented in a variety of ways. There is a one-to-many relationship at work here. From the point of view of the user interface these differences should not be detectable. This is another example of [hardware abstraction](/Computer_Architecture/Hardware_abstraction_and_modularity.md) ## NOT gate @@ -19,55 +42,61 @@ Physically, what 'travels through' the gates is electrical current and what cons ### Symbol -![](/img/not-gate-new.png) +![](/_img/not-gate-new.png) ### Truth conditions -| P | ~ P | -| --- | --- | -| T | F | -| F | T | +| $P$ | $\lnot P$ | +| --- | --------- | +| 1 | 0 | +| 0 | 1 | ### Interactive circuit + + ## AND gate > The AND gate represents the truth conditions of the [conjunction](/Logic/Truth-functional_connectives.md#conjunction) truth functional connective ### Symbol -![](/img/and-gate-new-2.png) +![](/_img/and-gate-new-2.png) ### Truth conditions -| P | Q | P & Q | -| --- | --- | ----- | -| T | T | T | -| T | F | F | -| F | T | F | -| F | F | F | +| $P$ | $Q$ | $P \land Q$ | +| --- | --- | ----------- | +| 1 | 1 | 1 | +| 1 | 0 | 0 | +| 0 | 0 | 0 | +| 0 | 0 | 0 | ### Interactive circuit + + ## NAND gate > The NAND gate inverts the truth conditions of AND. ### Symbol -![](/img/nand-gate-new.png) +![](/_img/nand-gate-new.png) ### Truth conditions -| P | Q | ~(P & Q) | -| --- | --- | -------- | -| T | T | F | -| T | F | F | -| F | T | F | -| F | F | T | +| $P$ | $Q$ | $\lnot(P \land Q)$ | +| --- | --- | ------------------ | +| 1 | 1 | 0 | +| 1 | 0 | 0 | +| 0 | 1 | 0 | +| 0 | 0 | 1 | ### Interactive circuit + + NAND is a **universal logic gate**: equipped with just a NAND we can represent every other possible logical condition. In practice with circuits, it is more efficient to use specific dedicated gates (i.e OR, AND, NOT etc) for the other Boolean connectives but in principle the same output can be achieved through NANDs alone. ## OR gate @@ -76,57 +105,59 @@ NAND is a **universal logic gate**: equipped with just a NAND we can represent e ### Symbol -![](/img/or-gate-new.png) +![](/_img/or-gate-new.png) ### Truth conditions -| P | Q | P v Q | -| --- | --- | ----- | -| T | T | T | -| T | F | T | -| F | T | T | -| F | F | F | +| $P$ | $Q$ | $P \lor Q$ | +| --- | --- | ---------- | +| 1 | 1 | 1 | +| 1 | 0 | 1 | +| 0 | 1 | 1 | +| 0 | 0 | 0 | ### Interactive circuit + + ## XOR gate > The OR gate represents the truth conditions of the exclusive OR ### Symbol -![](/img/xor-gate-new.png) +![](/_img/xor-gate-new.png) ### Truth conditions -| P | Q | ~(P <> Q) | -| --- | --- | --------- | -| T | T | F | -| T | F | T | -| F | T | T | -| F | F | F | +| $P$ | $Q$ | $\lnot(P \Leftrightarrow Q)$ | +| --- | --- | ---------------------------- | +| 1 | 1 | 0 | +| 1 | 0 | 1 | +| 0 | 1 | 1 | +| 0 | 0 | 0 | ### Interactive circuit + + ## NOR gate > The NOR gate inverts the function of an OR gate ### Symbol -![](/img/nor-gate-new.png) +![](/_img/nor-gate-new.png) ### Truth conditions -| P | Q | P v Q | -| --- | --- | ----- | -| T | T | F | -| T | F | F | -| F | T | F | -| F | F | T | +| $P$ | $Q$ | $P \lor Q$ | +| --- | --- | ---------- | +| 1 | 1 | 0 | +| 1 | 0 | 0 | +| 0 | 1 | 0 | +| 0 | 0 | 1 | ### Interactive circuit -## References - -Scott, J. Clark. 2009. _But how do it know?: the basic principles of computers for everyone_. Self-published. + diff --git a/Electronics_and_Hardware/Digital_circuits/Multiplexers_and_demultiplexers.md b/Electronics_and_Hardware/Digital_circuits/Multiplexers_and_demultiplexers.md new file mode 100644 index 0000000..2710a72 --- /dev/null +++ b/Electronics_and_Hardware/Digital_circuits/Multiplexers_and_demultiplexers.md @@ -0,0 +1,32 @@ +--- +categories: + - Electronics + - Hardware +tags: [logic-gates, binary, nand-to-tetris] +--- + +# Multiplexers (MUX) and demultiplexers (DMUX) + +## Multiplexer + +> Multiplexing is the generic term used to describe the operation of sending one or more analogue or digital signals over a common transmission line at different times or speeds. + +A multiplexer selects one of several input signals and forwards ths selected input to a single output line. + +We have two inputs (A,B) plus a third input SEL (for "select"). Applying a value to SEL toggles the output between A and B. + +Multiplexers can be used to build larger circuits by connecting the output of one multiplexer to the input of another. They are often used to implement data selection and switching in digital systems + +// TODO: Add component diagram + +### Programable gates + +One of the main use cases of multiplexers is to implement programmable gates. These are gates where the logic can be switched. For example an ANDMUXOR gate uses the SEL value to toggle the operation of a gate between AND and OR for its two inputs A and B + +## Demultiplexer + +As the name suggests, a demultiplexer reverses the functionality of a multiplexer. It receives a single input and based on the selection of the SEL input it channels it to either an A or a B output. + +We can think of it as a distributor of a value into one of several possible channels. + +// TODO: Add component diagram diff --git a/Electronics_and_Hardware/Digital_circuits/Three_bit_counter.md b/Electronics_and_Hardware/Digital_circuits/Three_bit_counter.md index 65d2636..9b1e373 100644 --- a/Electronics_and_Hardware/Digital_circuits/Three_bit_counter.md +++ b/Electronics_and_Hardware/Digital_circuits/Three_bit_counter.md @@ -44,7 +44,7 @@ If we look at the pattern of each flip-flops' output we notice the following: This means that to construct a circuit that displays this behaviour we just have to use a [T flip-flop](/Electronics_and_Hardware/Digital_circuits/Flip_flops.md#t-flip-flops) since the only state change we need is a single bit toggle three times that retains its value. Using these pulse patterns we can construct a circuit as follows: -![](/img/3-bit-adder-diagram.png) +![](/_img/3-bit-adder-diagram.png) diff --git a/Electronics_and_Hardware/Digital_circuits/Transistors.md b/Electronics_and_Hardware/Digital_circuits/Transistors.md index 2f350db..8df94c3 100644 --- a/Electronics_and_Hardware/Digital_circuits/Transistors.md +++ b/Electronics_and_Hardware/Digital_circuits/Transistors.md @@ -16,11 +16,11 @@ An electrical switch is inherently binary. When the switch is on, it acts like a We can combine switches in a circuit to create analogs to logic gates. -![](/img/switch-and-gate.png) +![](/_img/switch-and-gate.png) In the example above a simple AND gate is implemented with switches. Each switch is a conjunct and the current only flows if both switches are on, closing the circuit. -![](/img/switch-or-gate.png) +![](/_img/switch-or-gate.png) In the example above is a circuit implementing an OR gate. The current flows just if one of the switches are on or if both of the switches are on but not if both switches are off. @@ -32,15 +32,15 @@ Thus instead of switches, modern digital circuits use transistors, a special ele There are different types of transistors but the simplest for the purposes of explanation are **bipolar junction transistors**. -![](/img/transistor-diag.svg) +![](/_img/transistor-diag.svg) A transistor works as follows: applying a small amount of current at the base allows a larger current to flow from the collector to the emitter. Relating this back to switches, applying current to the base is like turning the switch on. Removing this current is like turning the switch off. The diagrams below show a transistor being used in a circuit to create 'on' and 'off' switch states alongside a switch based circuit. -![](/img/transistor-off.png) +![](/_img/transistor-off.png) -![](/img/transistor-on.png) +![](/_img/transistor-on.png) - $V^{in}$ is the voltage that electrically controls the switch-as-transistor - $V^{out}$ is the voltage we want to control: it will be high when the transistor is in the 'on' state and low otherwise @@ -60,8 +60,8 @@ With the basic element of the transistor established, we can combine transistors For example to create an [AND](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md#and-gate) gate we would have two voltage inputs going into two transistors that are connected in sequence. The two transistors create a continuous line going from the collector of one to the emitter of the other. If either voltage input is low then the voltage of the combined line is low (equivalent to the circuit being broken) and there is no current flowing. -![](/img/and-transistor.png) +![](/_img/and-transistor.png) Below, an [OR](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md#or-gate) has been constructed with transistors. If a voltage is applied to the base of either transistor, the current reaches the V-out terminal. -![](/img/or-transistor.svg) +![](/_img/or-transistor.svg) diff --git a/Electronics_and_Hardware/Motherboard.md b/Electronics_and_Hardware/Motherboard.md index c980d50..b55bb54 100644 --- a/Electronics_and_Hardware/Motherboard.md +++ b/Electronics_and_Hardware/Motherboard.md @@ -7,7 +7,7 @@ tags: [motherboard] # Motherboard - + The motherboard is the foundation of a computer. It allocates power and allows communication to and between the [CPU](/Computer_Architecture/CPU/Von_Neumann_architecture.md), [RAM](/Computer_Architecture/Memory/Memory.md), [harddisk](/Operating_Systems/Disks/What_are_disks.md) and all other hardware components. diff --git a/Electronics_and_Hardware/Physics_of_electricity/Electromagnetism.md b/Electronics_and_Hardware/Physics_of_electricity/Electromagnetism.md index 7a2abe0..267f4d2 100644 --- a/Electronics_and_Hardware/Physics_of_electricity/Electromagnetism.md +++ b/Electronics_and_Hardware/Physics_of_electricity/Electromagnetism.md @@ -32,7 +32,7 @@ Magnetism, understood as the effect of a magnetic field, arises from the propert As they spin they produce a **magnetic dipole**: the two poles noted above. We call this propensity of electrons the **intrinsic magnetic moment** of the electron. It is aggregates of these miniature magnetic behaviours that produce the overall magnetic property of the material. -![](/img/dipole-again.svg) +![](/_img/dipole-again.svg) In most materials, equal numbers of electrons spin in opposite directions. As a result, their magentic effects are cancelled out. However **in strongly magnetic materials an overall majority of electrons spin in one particular direction**. This breaks the equilibrium and produces the magnetic field. @@ -72,7 +72,7 @@ The magnetic field and force is more complex than the electric field/force. Wher This is illustrated below which shows the magnetic field operating at right angles to the flow of charge within a wire. - + ## The electromagnetic field @@ -101,7 +101,7 @@ Maxwell's Equations describe how electromagnetic fields are generated and behave Electromagnetic waves consist of rapidly changing electric and magnetic fields. They are emitted any time an electrically charged particle accelerates. These waves are generally referred to as light. However, more accurately, 'light' refers to the types of electromagnetic wave that we can see. Electromagnetic waves form a spectrum based on their frequency and wavelength. For example, 'radio waves' are low-frequency / long wavelength electromagnetic waves and gamma rays are high-frequency / short wavelength waves: -![](/img/em-spectrum.jpg) +![](/_img/em-spectrum.jpg) The image below shows the propagation of an electromagnetic wave through space. We can identify the core components as follows @@ -109,7 +109,7 @@ The image below shows the propagation of an electromagnetic wave through space. - The magenetic field is perpendicular to the vector of the electric field $E$ which propagates upward along the $y$ axis - The directionality of both waves is forward along the $x$ axis -![](/img/em-wave.gif) +![](/_img/em-wave.gif) ## Using magnetism to generate electricity diff --git a/Electronics_and_Hardware/Physics_of_electricity/Electrons.md b/Electronics_and_Hardware/Physics_of_electricity/Electrons.md index 70ab6f5..8295448 100644 --- a/Electronics_and_Hardware/Physics_of_electricity/Electrons.md +++ b/Electronics_and_Hardware/Physics_of_electricity/Electrons.md @@ -14,7 +14,7 @@ Each shell can accomodate a maximum number of electrons. The shells are designat _The diagram below demonstrates shell naming conventions and the maximum number of electrons per shell._ -![](/img/valence-shell.svg) +![](/_img/valence-shell.svg) ## Valence diff --git a/Electronics_and_Hardware/Physics_of_electricity/Matter_and_atoms.md b/Electronics_and_Hardware/Physics_of_electricity/Matter_and_atoms.md index 75a90b8..7b60cf9 100644 --- a/Electronics_and_Hardware/Physics_of_electricity/Matter_and_atoms.md +++ b/Electronics_and_Hardware/Physics_of_electricity/Matter_and_atoms.md @@ -22,7 +22,7 @@ tags: [physics] ## Atomic particles - + * There are three particles comprising atoms: **protons**, **neutrons** and **electrons**. diff --git a/Linux/Monitoring_processes_and_resources.md b/Linux/Monitoring_processes_and_resources.md index 26a7fc8..d22ae8f 100644 --- a/Linux/Monitoring_processes_and_resources.md +++ b/Linux/Monitoring_processes_and_resources.md @@ -16,7 +16,7 @@ We can use [ps](/Programming_Languages/Shell_Scripting/Processes.md) to list the _Here I have pressed `u` to show only the processes associated with my user:_ -![](/img/htop.png) +![](/_img/htop.png) ### Main commands @@ -96,7 +96,7 @@ procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- `lsof` stands for _list open files_. It lists opened files and the processes using them. Without modifiers it outputs a huge amount of data. The best way to use it is to execute it against a specific PID. For example the below output gives me some useful info about which files VS Code is using: -![](/img/lsof.png) +![](/_img/lsof.png) ## System calls: `strace` diff --git a/Linux/journald.md b/Linux/journald.md index b6c6ea8..fffaa62 100644 --- a/Linux/journald.md +++ b/Linux/journald.md @@ -8,7 +8,7 @@ tags: [journaling, systemd, systems-programming] `journald` is a program that comes as default with [systemd](/Linux/systemd.md). It is a service fror collecting and storing system-level log data. I keeps a track of all [kernel](/Operating_Systems/The_Kernel.md) processes. It is invaluable when tracing the source of problems and errors that may arise on the system level. It keeps a track of all kernal processes. -![](/img/journald.png) +![](/_img/journald.png) ## `journalctl` diff --git a/Linux/systemd.md b/Linux/systemd.md index b3268c8..c622bb4 100644 --- a/Linux/systemd.md +++ b/Linux/systemd.md @@ -51,13 +51,13 @@ Units are managed via `systemd` configuration files. System level `systemd` config files are located in the _system unit directory_ at `/usr/lib/systemd/system`. You shouldn't change or manipulate these files or attempt to add new config files here since they will be overwritten by the system. -![](/img/systemd-global-files.png) +![](/_img/systemd-global-files.png) _`systemd` global unit files_ Local definitions that relate to the specific user and where the user herself can define units are located in the _system configuration_ directory: `/etc/systemd/system`. -![](/img/systemd-local-files.png) +![](/_img/systemd-local-files.png) _`systemd` local unit files, specific to the currently logged-in user_ diff --git a/Logic/General_concepts/Consistency.md b/Logic/General_concepts/Consistency.md deleted file mode 100644 index 45e8d8c..0000000 --- a/Logic/General_concepts/Consistency.md +++ /dev/null @@ -1,63 +0,0 @@ ---- -categories: - - Mathematics -tags: [logic] ---- - -## Informal definition - -A set of sentences is consistent if and only if **it is possible for all the members of the set to be true at the same time**. A set of sentences is inconsistent if and only if it is not consistent. - -### Demonstration - -The following set of sentences form an inconsistent set: - -``` -(1) Anyone who takes astrology seriously is a lunatic. -(2) Alice is my sister and no sister of mine has a lunatic for a husband. -(3) David is Alice's husband and he read's the horoscope column every morning. -(4) Anyone who reads the horoscope column every morning takes astrology seriously. -``` - -The set is inconsistent because not all of them can be true. If (1), (3), (4) are true, (2) cannot be. If (2), (3),(4) are true, (1) cannot be. - -## Formal definition - -> A finite set of sentences $\Gamma$ is truth-functionally consistent if and only if there is at least one truth-assignment in which all sentences of $\Gamma$ are true. - -### Informal expression - -``` -The book is blue or the book is brown -The book is brown -``` - -### Formal expression - -``` -{P v Q, Q} -``` - -### Truth-table - -``` -P Q P ∨ Q Q -T T T T * -T F T F -F T T T * -F F F F -``` - -## Derivation - -> In terms of logical derivation, a finite $\Gamma$ of propositions is **inconsistent** in a system of derivation for propositional logic if and only if a sentence of the $P & \sim P$ is derivable from $\Gamma$. It is **consistent** just if this is not the case. - -In other terms, if you can derive a contradiction from the set, the set is logically inconsistent. - -A [contradiction](Logical%20truth%20and%20falsity.md#logical-falsity) contradiction has very important consequences for reasoning because if a set of propositions is inconsistent, every and all other propositions are derivable from that set. - -![proofs-drawio-Page-5.drawio 3.png](../img/proofs-drawio-Page-5.drawio%203.png) - -_A demonstration of the the consequences of deriving a contradiction in a sequence of reasoning._ - -Here we want to derive some proposition $Q$. If we can derive a contradiction from its negation as an assumption then, by the [negation elimination](Negation%20Elimination.md) rule, we can assert $Q$. This is why contradictions should be avoided in arguments, they 'prove' everything which, by association, undermines any particular premise you are trying to assert. diff --git a/Logic/General_concepts/Indeterminacy.md b/Logic/General_concepts/Indeterminacy.md deleted file mode 100644 index f44eaca..0000000 --- a/Logic/General_concepts/Indeterminacy.md +++ /dev/null @@ -1,49 +0,0 @@ ---- -categories: - - Mathematics -tags: [logic] ---- - -The vast majority of sentences in natural and formal logical languages are neither [ logically true](Logical%20truth%20and%20falsity.md#logical-truth) or [\| logically false](Logical%20truth%20and%20falsity.md#logical-falsity). This makes sense because sentences of this form are all either tautologies or contradictions and as such do not express information about the state of events in the world. We call sentences that are neither logically true or logically false, logically indeterminate sentences. - -## Informal definition - -A sentence is logically indeterminate if it is neither logically true or logically false. This is to say: it can be both [consistently](Consistency.md) asserted and consistently denied. - -For example the sentence: - -``` -It is raining. -``` - -May be true or false thus it can it both be asserted and denied quite consistently. It is true if it actually is raining and false if it actually is not raining. There is no logical contradiction in saying it is raining when it isn't raining, this assertion is simply false. There is a contradiction in saying it is both states. Thus the sentence: - -``` -It is raining and it is not raining. -``` - -Cannot be consistently asserted as there is no possibility of the sentence being true. It is either raining or it isn't raining. Given the law for conjunction both conjuncts must be true for the sentence as a whole to be true. But in the case of this sentence if one conjunct is true, the other must be false and vice versa, hence it is not possible for the sentence to be true at all. It can _only_ be false. - -Contrariwise the sentence: - -``` -It is raining or it is not raining. -``` - -Cannot be consistently denied as there is no possibility of it being false. It is either raining or not raining. Given the law for disjunction, either disjunct can be true to make the sentence as a whole true. Given that it is either raining or not raining in either scenario, the sentence as a whole will be true. Therefore there is no possibility of it being false, it can _only_ be true. - -## Formal definition - -> A sentence P is truth-functionally indeterminate if and only if it is neither truth-functionally true or truth-functionally false. - -``` -P -``` - -### Truth-table - -``` -P P -T T -F F -``` diff --git a/Logic/General_concepts/Logical_consistency.md b/Logic/General_concepts/Logical_consistency.md new file mode 100644 index 0000000..371d430 --- /dev/null +++ b/Logic/General_concepts/Logical_consistency.md @@ -0,0 +1,64 @@ +--- +categories: + - Logic +tags: [propositional-logic] +--- + +# Logical consistency + +## Informal definition + +A set of propositions is consistent if and only if **it is possible for all the members of the set to be true at the same time**. A set of propositions is inconsistent if and only if it is not consistent. + +### Demonstration + +The following set of propositions form an inconsistent set: + +1. Anyone who takes astrology seriously is a lunatic. +2. Alice is my sister and no sister of mine has a lunatic for a husband. +3. David is Alice's husband and he read's the horoscope column every morning. +4. Anyone who reads the horoscope column every morning takes astrology seriously. + +The set is inconsistent because not all of them can be true. If (1), (3), (4) are true, (2) cannot be. If (2), (3),(4) are true, (1) cannot be. + +## Formal definition + +> A finite set of propositions $\Gamma$ is truth-functionally consistent if and only if there is at least one truth-assignment in which all propositions of $\Gamma$ are true. + +### Informal expression + +``` +The book is blue or the book is brown +The book is brown +``` + +### Formal expression + +$$ +\{P \lor Q, Q\} +$$ + +### Truth table + +$ \{P, Q\} $ form a consistent set because there is at least one assignment when both propositions are true. In fact there are two (corresponding to each disjunct) but one is sufficient. + +| $P$ | $Q$ | $ P \lor Q $ | $Q$ | +| --- | --- | ------------ | --- | +| T | T | T | T | +| T | F | T | F | +| F | T | T | T | +| F | F | F | F | + +## Derivation + +> In terms of logical derivation, a finite $\Gamma$ of propositions is **inconsistent** in a system of derivation for propositional logic if and only if a proposition of the form $P \& \lnot P$ is derivable from $\Gamma$. It is **consistent** just if this is not the case. + +In other terms, if you can derive a contradiction from the set, the set is logically inconsistent. + +A [contradiction](/Logic/General_concepts/Logical_truth_and_falsity.md#logical-falsity) has very important consequences for reasoning because if a set of propositions is inconsistent, any other proposition is derivable from it. + +![](/_img/derivation_from_contradiction.png) + +_A demonstration of the the consequences of deriving a contradiction in a sequence of reasoning._ + +Here we want to derive some proposition $Q$. If we can derive a contradiction from its negation as an assumption then, by the [negation elimination](/Logic/Proofs/Negation_Elimination.md)) rule, we can assert $Q$. This is why contradictions should be avoided in arguments, they 'prove' everything which, by association, undermines any particular premise you are trying to assert. diff --git a/Logic/General_concepts/Logical_equivalence.md b/Logic/General_concepts/Logical_equivalence.md index d6ffd39..f205dd3 100644 --- a/Logic/General_concepts/Logical_equivalence.md +++ b/Logic/General_concepts/Logical_equivalence.md @@ -1,48 +1,38 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- +# Logical equivalence + > Two sentences, P and Q, are truth-functionally equivalent if and only if there is no truth assignment in which P is true and Q is false ### Informal expression -``` P: If it is raining then the pavement will be wet. + Q: The pavement is not wet unless it is raining. -``` ### Formal expression $$ -P \supset Q \equiv \sim P \lor Q +(P \rightarrow Q) \longleftrightarrow (\lnot P \lor Q) $$ ### Truth-tables -``` -P Q P ⊃ Q -T T T -T F F -F T T -F F T -``` - -``` -P Q ~ P ∨ Q -T T T -T F F -F T T -F F T -``` +| $P$ | $Q$ | $ P \rightarrow Q $ | $ \lnot P \lor Q$ | +| --- | --- | ------------------- | ----------------- | +| T | T | T | T | +| T | F | T | F | +| F | T | T | T | +| F | F | F | T | ### Derivation > Propositions $P$ and $Q$ are equivalent in a system of [derivation](Formal%20proofs%20in%20propositional%20logic.md) for propositional logic if $Q$ is derivable from $P$ and $P$ is derivable from $Q$. -Note that the property of equivalence stated in terms of derivablity above is identical to the derivation rule for the [material biconditional](Biconditional%20Introduction.md): +Note that the property of equivalence stated in terms of derivablity above is identical to the derivation rule for the [material biconditional](/Logic/Proofs/Biconditional_Introduction.md): -![bi-intro.png](../img/bi-intro.png) - -//TODO: Add demonstration of this by deriving two equivalents from one of DeMorgan's Laws +![bi-intro.png](/_img/bi-intro.png) diff --git a/Logic/General_concepts/Logical_indeterminacy.md b/Logic/General_concepts/Logical_indeterminacy.md new file mode 100644 index 0000000..3fc4722 --- /dev/null +++ b/Logic/General_concepts/Logical_indeterminacy.md @@ -0,0 +1,51 @@ +--- +categories: + - Logic +tags: [propositional-logic] +--- + +# Logical indeterminacy + +The vast majority of propositions in natural and formal logical languages are **neither [logically true](/Logic/General_concepts/Logical_truth_and_falsity.md#logical-truth) or [logically false](/Logic/General_concepts/Logical_truth_and_falsity.md#logical-falsity)**. This makes sense because propositions of this form are all either tautologies or contradictions and as such do not express information about the state of events in the world. We call propositions that are neither logically true or logically false, **logically indeterminate** propositions. + +## Informal definition + +A proposition is logically indeterminate if it is neither logically true or logically false. This is to say: it can be both [consistently](Consistency.md) asserted and consistently denied. + +For example the proposition: + +``` +It is raining. +``` + +May be true or false thus it can it both be asserted and denied quite consistently. It is true if it actually is raining and false if it actually is not raining. There is no logical contradiction implied by saying it is raining when it isn't raining, this assertion is simply false. There is a contradiction in saying that both states obtain. Thus the proposition: + +``` +It is raining and it is not raining. +``` + +Cannot be consistently asserted as there is no possibility of the proposition being true. It is either raining or it isn't raining. Given the law for conjunction, both conjuncts must be true for the proposition as a whole to be true. But in the case of this proposition if one conjunct is true, the other must be false and vice versa, hence it is not possible for the proposition to be true at all. It can _only_ be false. + +Contrariwise the proposition: + +``` +It is raining or it is not raining. +``` + +Cannot be consistently denied as there is no possibility of it being false. It is either raining or not raining. Given the law for disjunction, either disjunct can be true to make the proposition as a whole true. Given that it is either raining or not raining in either scenario, the proposition as a whole will be true. Therefore there is no possibility of it being false, it can _only_ be true. + +## Formal definition + +> A proposition P is truth-functionally indeterminate if and only if it is neither truth-functionally true or truth-functionally false. +> should be avoided in arguments, they 'prove' everything whi + +``` +P +``` + +### Truth-table + +| $P$ | $P$ | +| --- | --- | +| T | T | +| F | F | diff --git a/Logic/General_concepts/Logical_possibility_and_necessity.md b/Logic/General_concepts/Logical_possibility_and_necessity.md index 19a7d31..45e4602 100644 --- a/Logic/General_concepts/Logical_possibility_and_necessity.md +++ b/Logic/General_concepts/Logical_possibility_and_necessity.md @@ -1,12 +1,14 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- +# Logical possibility and necessity + ## Logical possibility -In distinguishing the properties of [logical consistency](Consistency.md) and [validity](Validity%20and%20entailment.md#validity) we make tacit use of the notion of **possibility**. This is because when we consider the validity of an argument we are assessing truth-conditions and this consists in asking ourselves what could or could not be the case: were it such that _P_, then it would be the case that _Q_. It is important to understand what possibility means in the context of logic and how it differs from what we might mean ordinarily when we use the term. +In distinguishing the properties of [logical consistency](/Logic/General_concepts/Logical_consistency.md) and [validity](/Logic/General_concepts/Validity_and_entailment.md) we make tacit use of the notion of **possibility**. This is because when we consider the validity of an argument we are assessing truth-conditions and this consists in asking ourselves what could or could not be the case: were it such that _P_, then it would be the case that _Q_. It is important to understand what possibility means in the context of logic and how it differs from what we might mean ordinarily when we use the term. It is evident from the case of arguments that are valid but not sound that logic operates with a specialised notion of possibility. For example it has to be the case that the proposition _Every woman can levitate_ is logically possible since the following argument is valid: @@ -32,6 +34,6 @@ From this we can derive the following property of logical possibility: ## Logical necessity -A sentence is _logically necessary_ if it is true in every logically possible circumstance which is to say: true on every possible truth functional assignment. Necessity and [ logical truth](Logical%20truth%20and%20falsity.md#logical-truth) are therefore synonyms: anything that is logically true (a tautology) is true by necessity (could not be otherwise.) +A proposition is _logically necessary_ if it is true in every logically possible circumstance which is to say: true on every possible truth functional assignment. Necessity and [logical truth](/Logic/General_concepts/Logical_truth_and_falsity.md#logical-truth) are therefore synonyms: anything that is logically true (a tautology) is true by necessity (could not be otherwise.) Further, every logical truth is logically possible but not everything that is logically possible is logically true. It is possible that it is raining but this is not logically necessary - it could be otherwise, i.e not raining. However it is not possible that it could be both raining and not raining. diff --git a/Logic/General_concepts/Logical_truth_and_falsity.md b/Logic/General_concepts/Logical_truth_and_falsity.md index 5b701d9..3baa2b8 100644 --- a/Logic/General_concepts/Logical_truth_and_falsity.md +++ b/Logic/General_concepts/Logical_truth_and_falsity.md @@ -1,16 +1,18 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -We say of certain sentences that they are logically true or logically false. +# Logical truth and falsity + +We say of certain propositions that they are logically true or logically false. ## Logical falsity ### Informal definition -A sentence is logically false if and only if **it is not possible for the sentence to be true**. The sentence itself cannot be consistently asserted. +A proposition is logically false if and only if **it is not possible for the proposition to be true**. The proposition itself cannot be consistently asserted. **Demonstration** @@ -19,9 +21,7 @@ There is a country that is not a country. Apples are fruits and apples are not fruits ``` -Neither sentence can be true because the truth of the first clause is contradicted by the second. By the principle of [consistency](Consistency.md), it is not possible for both clauses to be true at once therefore the sentence, overall has the truth value of falsity - -The examples above are simple sentences but logical falsity also applies to compound sentences and it is actually easier to see the logical principle at work with compound sentences since once simple sentence of the compound contradicts the other such that the overall sentence cannot be consistently asserted: +Neither proposition can be true because the truth of the first clause is contradicted by the second. By the principle of [consistency](/Logic/General_concepts/Logical_consistency.md), it is not possible for both clauses to be true at once therefore the proposition, overall has the truth value of false. ``` It is raining and it is not raining. @@ -29,28 +29,24 @@ It is raining and it is not raining. ### Formal definition -> A sentence P is truth-functionally false if and only if P is false on every truth-value assignment +> A proposition P is truth-functionally false if and only if P is false on every truth-value assignment ### Formal expression -``` -P & ~ P -``` +$$ P \land \lnot P $$ ### Truth-table -``` - Can -P P & ~ P -T F -F F -``` +| $P$ | $P \land \lnot P$ | +| --- | ----------------- | +| T | F | +| T | F | ## Logical truth ### Informal definition -A sentence is logically true if and only if it is not possible for the sentence to be false. The sentence itself cannot be [consistently](Consistency.md) denied. +A proposition is logically true if and only if it is not possible for the proposition to be false. The proposition itself cannot be consistently denied. **Demonstration** @@ -59,35 +55,32 @@ A rose is a rose. Today is Tuesday unless today is not Tuesday. ``` -Regardless of any facts obtaining in the world, these sentences cannot be false. +Regardless of any facts obtaining in the world, these propositions cannot be false.should be avoided in arguments, they 'prove' everything whi -As with logically false sentences, logical truth can also apply to compound sentences: +As with logically false propositions, logical truth can also apply to compound propositions: ``` -It is Monday and Monday is a day of the week. +A rose is a rose and a shoe is a shoe ``` ### Formal definition -> A sentence P is truth-functionally true if and only if P is true on every truth-value assignment +> A proposition P is truth-functionally true if and only if P is true on every truth-value assignment -``` -P v ~P -``` +$$ P \lor \lnot P$$ ### Truth-table -``` -P P ∨ ¬ P -T T -F T -``` +| $P$ | $P \lor \lnot P$ | +| --- | ---------------- | +| T | T | +| F | T | ### Consequences -The existence of logically false and logically true sentences affects the validity and soundness of arguments in which they are used. These are technicalities that have philosophically interesting consequences. +The existence of logically false and logically true propositions affects the validity and soundness of arguments in which they are used. These are technicalities that have philosophically interesting consequences. -- If an argument contains premises which are logically false than this argument will perforce be valid. This is because one cannot consistently assert the premises and deny the conclusion which is the definition of validity. However the _reason_ why one cannot consistently assert the premises and deny the conclusions is because one cannot consistently assert the premises - they conflict with each other. Furthermore as the argument contains false premises, it cannot be sound. +- If an argument contains premises which are logically false than this argument will perforce be valid. This is because one cannot consistently assert the premises and deny the conclusion which is the definition of [validity](/Logic/General_concepts/Validity_and_entailment.md). However the _reason_ why one cannot consistently assert the premises and deny the conclusions is because one cannot consistently assert the premises - they conflict with each other. Furthermore as the argument contains false premises, it cannot be sound. ``` (P1) Russia is a country. diff --git a/Logic/General_concepts/Object_language_and_meta-language.md b/Logic/General_concepts/Object_language_and_meta-language.md index 1cb6df8..5bb5ebf 100644 --- a/Logic/General_concepts/Object_language_and_meta-language.md +++ b/Logic/General_concepts/Object_language_and_meta-language.md @@ -1,10 +1,10 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -## Object and metalanguages +# Object and metalanguages When we talk about a language we call that language the **object language**. A **metalanguage** is a language used to describe some object language. @@ -28,4 +28,4 @@ When we create an expression in a language we are said to _use_ that language. W A metalinguistic variable (metavariable for short) is an expression in the metalanguage that is used to talk generally about expressions of the object language. The convention in these notes will be to embolden single letters when these letters are used as metavariables. -For example, instead of saying _'P & Q' is an expression comprising two atomic sentences and a conjunction_ we might say **\*P** is an expression comprising two atomic sentences and a conjunction.\* In this instance **P** is a metavariable in the metalanguage mentioning the expression P & Q in the object language +For example, instead of saying _'P & Q' is an expression comprising two atomic sentences and a conjunction_ we might say **\*P** is an expression comprising two atomic sentences and a conjunction. In this instance **P** is a metavariable in the metalanguage mentioning the expression P & Q in the object language diff --git a/Logic/General_concepts/Soundness.md b/Logic/General_concepts/Soundness.md index 0c78a73..80b84b5 100644 --- a/Logic/General_concepts/Soundness.md +++ b/Logic/General_concepts/Soundness.md @@ -1,12 +1,12 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -### Soundness +# Soundness -Recall that in the definition of [deductive validity](Validity%20and%20entailment.md#validity) we do not say: an argument is valid iff if the premises _are true_ and the conclusion _is true_. We say _if it is possible for the premises to be true_. This is important: we are not interested in the actual truth of the premises or the conclusion. +Recall that in the definition of [deductive validity](/Logic/General_concepts/Validity_and_entailment.md#validity) we do not say: an argument is valid iff if the premises _are true_ and the conclusion _is true_. We say _if it is possible for the premises to be true_. This is important: we are not interested in the actual truth of the premises or the conclusion. #### Demonstration @@ -32,20 +32,19 @@ ____________________________________________ The difference here is that the premises happen to be true and, given that the argument is valid, the conclusion must also be true. What we have defined here is **soundness**: the argument is said to be sound as well as valid. This is an additional and stronger criterion of evaluation. -> An argument is sound if and only if it is deductively valid and all it's premises are true. +> An argument is sound if and only if it is deductively valid and all its premises are true. We must not forget that truth alone is not the sole condition for soundness. We can have arguments whose conclusion and premises are all true without the argument being sound: ``` (P1) London is the capital of the United Kingdom (P2) The capital of the United Kingdom is in the southern part of the United Kingdom. - Can (P3) Cambridge is not the capital of the United Kingdom ____________________________________________ (C) London is south of Cambridge ``` -All sentences are true here but the argument is not deductively valid: the premises are all true but the conclusion is false. +All propositions are true here but the argument is not deductively valid: the premises are all true but the conclusion is false. We can also have arguments which are valid but which are not sound: @@ -56,4 +55,4 @@ ____________________________________________ (C) Vitamin C is harmless ``` -This argument is valid because we cannot consistently assert the premises and deny the conclusion. In either case, the conclusion can be said to follow from the premises. The problem is that we cannot consistently assert both premises: it is not possible for both sentences to be true at the same time. +This argument is valid because we cannot consistently assert the premises and deny the conclusion. In either case, the conclusion can be said to follow from the premises. The problem is that we cannot consistently assert both premises: it is not possible for both propositions to be true at the same time. diff --git a/Logic/General_concepts/Syllogism.md b/Logic/General_concepts/Syllogism.md index e7b8db0..6911386 100644 --- a/Logic/General_concepts/Syllogism.md +++ b/Logic/General_concepts/Syllogism.md @@ -1,12 +1,14 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -In order to make assertions about the relative [consistency](Consistency.md) or inconsistency of a set of propositions we advance arguments. Consider everyday life: if we are having an argument with someone, we believe that they are wrong. A more logical way to say this is that we believe that their beliefs are inconsistent. In order to change their viewpoint or point out why they are wrong we advance an argument intended to show that belief A conflicts with belief B. Or if C is true, then you cannot believe that D. +# Syllogism -In formal terms **an argument is a set of sentences comprising one or more premises and a conclusion. The conclusion is taken to be supported by the premises.** +In order to make assertions about the relative [consistency](/Logic/General_concepts/Logical_consistency.md) or inconsistency of a set of propositions we advance arguments. Consider everyday life: if we are having an argument with someone, we believe that they are wrong. A more logical way to say this is that we believe that their beliefs are inconsistent. In order to change their viewpoint or point out why they are wrong we advance an argument intended to show that belief A conflicts with belief B. Or if C is true, then you cannot believe that D. + +In formal terms **an argument is a set of propositions comprising one or more premises and a conclusion. The conclusion is taken to be supported by the premises.** > The terms **argument** and **syllogism** are used interchangeably in logic to describe the above feature of a set of propositions. diff --git a/Logic/General_concepts/Validity_and_entailment.md b/Logic/General_concepts/Validity_and_entailment.md index ef91b89..9d4241d 100644 --- a/Logic/General_concepts/Validity_and_entailment.md +++ b/Logic/General_concepts/Validity_and_entailment.md @@ -1,7 +1,7 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- ## Validity @@ -39,23 +39,21 @@ The test for a strong inductive argument is not whether the conclusion is true, > An argument is truth-functionally valid if and only if there is no truth-assignment on which all the premises are true and the conclusion is false. -Linking this to [derivation](Formal%20proofs%20in%20propositional%20logic.md), we say: +Linking this to derivation, we say: > In a system of derivation in propositional logic, an argument is valid if the conclusion of the argument is derivable within the system of derivation from the set consisting of the premises, and invalid otherwise. ### Demonstration -The inference from the set ${P, P \supset Q}$ to $Q$ is valid +The inference from the set ${P, P \rightarrow Q}$ to $Q$ is valid ### Truth-table -``` -P Q P ⊃ Q P Q -T T T T T * -T F F T F -F T T F T -F F T F F -``` +| $P$ | $Q$ | $P \rightarrow Q$ | $P$ | $Q$ | Assessment | +| --- | --- | ----------------- | --- | --- | ---------- | +| T | T | T | T | T | Valid | +| T | F | F | T | F | | +| F | T | T | F | T | | ## Entailment @@ -79,16 +77,14 @@ The pavement is wet. #### Formal demonstration -``` -{P, P ⊃ Q} ⊨ Q -``` +$$ + \{ P, P\rightarrow Q \} \vdash Q +$$ #### Truth-table -``` -P Q P ⊃ Q P Q -T T T T T * -T F F T F -F T T F T -F F T F F -``` +| $P$ | $Q$ | $P \rightarrow Q$ | $P$ | $Q$ | Assessment | +| --- | --- | ----------------- | --- | --- | ---------- | +| T | T | T | T | T | Valid | +| T | F | F | T | F | | +| F | T | T | F | T | | diff --git a/Logic/Laws_and_theorems.md/Corresponding_material_and_biconditional.md b/Logic/Laws_and_theorems.md/Corresponding_material_and_biconditional.md index 70c3bde..e6d79b6 100644 --- a/Logic/Laws_and_theorems.md/Corresponding_material_and_biconditional.md +++ b/Logic/Laws_and_theorems.md/Corresponding_material_and_biconditional.md @@ -1,41 +1,39 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -## Corresponding material conditional to show validity +# Corresponding material conditional to show validity To demonstrate _truth-functional validity_ we have to construct a truth-table which contains each of the premises and the conclusion and then review each row to see if there is an assignment where both the premises and the conclusion are true. -A simpler way to get the same result is to invoke the corresponding material conditional. Here we concatenate the premises using conjunction and then join them to the conclusion using the material conditional, which then becomes the main connective. We then populate the truth table for this compound sentence. If it is logically true, the argument is valid. +A simpler way to get the same result is to invoke the corresponding material conditional. Here we concatenate the premises using conjunction and then join them to the conclusion using the material conditional, which then becomes the main connective. We then populate the truth table for this compound proposition. If it is logically true, the argument is valid. ### Demonstration We will demonstrate with the following set: -$$ {P \equiv Q, P \lor Q, P &Q } $$ +$$ \{ P \leftrightarrow Q, P \lor Q, P \land Q \} $$ -``` -P Q P ≡ Q P ∨ Q P & Q -T T T T T * -T F F T F -F T F T F -F F T F F -``` +| $P$ | $Q$ | $P \leftrightarrow Q$ | $P \lor Q$ | +| --- | --- | --------------------- | ---------- | +| T | T | T | T | +| T | F | F | T | +| F | T | F | T | +| F | F | T | F | -``` -P Q ( ( P ≡ Q ) & ( P ∨ Q ) ) ≡ ( P & Q ) -T T T -T F T -F T T -F F T -``` +| $P$ | $Q$ | $(P \leftrightarrow Q) \land (P \lor Q)) \leftrightarrow (P \land Q)$ | +| --- | --- | --------------------------------------------------------------------- | +| T | T | T | +| T | F | T | +| F | T | T | +| F | F | T | We see above that the main connective, the material conditional returns true for every truth-functional assignment. In other words it is logically true. Consequently the argument is valid ## Corresponding material biconditional -We can use the corresponding material biconditional as a shorthand for demonstrating logical equivalence between two sentences. +We can use the corresponding material biconditional as a shorthand for demonstrating logical equivalence between two propositions. -For two putatively equivalent sentences $P$ and $Q$, $P$ and $Q$ are logically equivalent if the compound sentence $P \equiv Q$ is logically true. +For two putatively equivalent propositions $P$ and $Q$, $P$ and $Q$ are logically equivalent if the compound proposition $P \leftrightarrow Q$ is logically true. diff --git a/Logic/Laws_and_theorems.md/DeMorgan's_Laws.md b/Logic/Laws_and_theorems.md/DeMorgan's_Laws.md index d816931..bfd252a 100644 --- a/Logic/Laws_and_theorems.md/DeMorgan's_Laws.md +++ b/Logic/Laws_and_theorems.md/DeMorgan's_Laws.md @@ -6,26 +6,36 @@ tags: [logic, laws] # DeMorgan's Laws -DeMorgan's laws express some fundamental equivalences that obtain between the Boolean [connectives](Truth-functional%20connectives.md): +DeMorgan's laws express some fundamental equivalences that obtain between the Boolean [connectives](/Logic/Propositional_logic/Truth-functional_connectives.md). ## First Law > The negation of a conjunction is logically equivalent to the disjunction of the negations of the original conjuncts. $$ -\sim (P \& Q) \equiv \sim P \lor \sim Q +\lnot (P \land Q) \leftrightarrow \lnot P \lor \lnot Q $$ The equivalence is demonstrated with the following truth-table -![demorgan-1.png](/img/demorgan-1.png) +| $P$ | $Q$ | $ \lnot (P \land Q)$ | $ \lnot P \lor \lnot Q$ | +| --- | --- | -------------------- | ----------------------- | +| T | T | F | F | +| T | F | T | T | +| F | T | T | T | +| F | F | T | T | ## Second Law > The negation of a disjunction is equivalent to the conjunction of the negation of the original disjuncts. $$ -\sim (P \lor Q) \equiv \sim P \& \sim Q +\lnot (P \lor Q) \leftrightarrow \lnot P \land \lnot Q $$ -![demorgan-2.png](/img/demorgan-2.png) +| $P$ | $Q$ | $ \lnot (P \lor Q)$ | $ \lnot P \land \lnot Q$ | +| --- | --- | ------------------- | ------------------------ | +| T | T | F | F | +| T | F | F | F | +| F | T | F | F | +| F | F | T | T | diff --git a/Logic/Laws_and_theorems.md/Law_of_Non-Contradiction.md b/Logic/Laws_and_theorems.md/Law_of_Non-Contradiction.md index cdde0bb..106cd69 100644 --- a/Logic/Laws_and_theorems.md/Law_of_Non-Contradiction.md +++ b/Logic/Laws_and_theorems.md/Law_of_Non-Contradiction.md @@ -1,11 +1,13 @@ --- categories: - - Mathematics -tags: [logic, theorems] + - Logic +tags: [propositional-logic] --- +# Law of Non-Contradiction + > A proposition cannot be true and false at the same time. -> -> $$ -> \\sim (P & \sim P) -> $$ + +$$ +\lnot (P \land \lnot P) +$$ diff --git a/Logic/Laws_and_theorems.md/Law_of_the_Excluded_Middle.md b/Logic/Laws_and_theorems.md/Law_of_the_Excluded_Middle.md index 2a3c909..6a954b3 100644 --- a/Logic/Laws_and_theorems.md/Law_of_the_Excluded_Middle.md +++ b/Logic/Laws_and_theorems.md/Law_of_the_Excluded_Middle.md @@ -1,11 +1,13 @@ --- categories: - - Mathematics -tags: [theorems, logic] + - Logic +tags: [propositional-logic] --- +# Law of the Excluded Middle + > Every proposition has to be either true or false. There can be no middle ground. -> -> $$ -> P \lor \sim P -> $$ + +$$ +P \lor \sim P +$$ diff --git a/Logic/Laws_and_theorems.md/Theorems_and_empty_sets.md b/Logic/Laws_and_theorems.md/Theorems_and_empty_sets.md index 6d42776..efcd8fe 100644 --- a/Logic/Laws_and_theorems.md/Theorems_and_empty_sets.md +++ b/Logic/Laws_and_theorems.md/Theorems_and_empty_sets.md @@ -1,13 +1,14 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -We know that when we construct a [derivation](Formal%20proofs%20in%20propositional%20logic.md#constructing-proofs) we start from a set of assumptions and then attempt to reach a proposition that is a consequence of the starting assumptions. However it does not always have to be the case that the starting set contains members. The set can in fact be empty. +We know that when we construct a [derivation](/Logic/Proofs/Formal_proofs_in_propositional_logic.md#derivation-rules) we start from a set of assumptions and then attempt to reach a proposition that is a consequence of the starting assumptions. However it does not always have to be the case that the starting set contains members. The set can in fact be empty. _Demonstration_ -![proofs-drawio-Page-5.drawio 2.png](../img/proofs-drawio-Page-5.drawio%202.png) + +![](/_img/proofs-drawio-Page-5.drawio_2.png) We see in this example that there is no starting set and thus no primary assumptions. Instead we start with nothing other than the proposition we wish to derive. The proposition is effectively derived from itself. In these scenarios we say that we are constructing a derivation from an **empty set**. @@ -18,7 +19,7 @@ Propositions which possess this property are called theorems: We represent a theorem as: $$ -\\vdash P +\vdash P $$ (There is no preceding $\Gamma$ as the set is empty. ) diff --git a/Logic/Proofs/Biconditional_Elimination.md b/Logic/Proofs/Biconditional_Elimination.md index 7b71ca5..84ad332 100644 --- a/Logic/Proofs/Biconditional_Elimination.md +++ b/Logic/Proofs/Biconditional_Elimination.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- -Give that the biconditional means that if $P$ is the case, $Q$ is the case and if $Q$ is the case, $P$ must be the case, if we have $P \equiv Q$ and $P$, we can derive $Q$ and vice versa. +# Biconditional Elimination -![biconditional-elim.png](../img/biconditional-elim.png) +Give that the biconditional means that if $P$ is the case, $Q$ must be the case and if $Q$ is the case, $P$ must be the case, if we have $P \leftrightarrow Q$ and $P$, we can derive $Q$ and vice versa. + +![](/_img/biconditional-elim.png) diff --git a/Logic/Proofs/Biconditional_Introduction.md b/Logic/Proofs/Biconditional_Introduction.md index e864f16..cef1d4b 100644 --- a/Logic/Proofs/Biconditional_Introduction.md +++ b/Logic/Proofs/Biconditional_Introduction.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [] + - Logic +tags: [derivation-rules] --- -The biconditional means if $P$ is the case, $Q$ is the case and if $Q$ is the case, $P$ must be the case. Thus to introduce this operator we must demonstrate both that $Q$ follows from $P$ and that $P$ follows from $Q$. We do this via two sub-proofs. +# Biconditional introduction -![bi-intro.png](../img/bi-intro.png) +The biconditional means if $P$ is the case, $Q$ must be the case and if $Q$ is the case, $P$ must be the case. Thus to introduce this operator we must demonstrate both that $Q$ follows from $P$ and that $P$ follows from $Q$. We do this via two sub-proofs. + +![](/_img/bi-intro.png) diff --git a/Logic/Proofs/Conditional_Elimination.md b/Logic/Proofs/Conditional_Elimination.md index 1a3672a..5e44711 100644 --- a/Logic/Proofs/Conditional_Elimination.md +++ b/Logic/Proofs/Conditional_Elimination.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- +# Conditional elimination + If we have a conditional and we have independently derived its antecedent, we may invoke its consequent. This is often referred to as _Modus ponens_ (affirming the antecedent). -![cond-elim.png](../img/cond-elim.png) +![](/_img/cond-elim.png) diff --git a/Logic/Proofs/Conditional_Introduction.md b/Logic/Proofs/Conditional_Introduction.md index c522575..92aa925 100644 --- a/Logic/Proofs/Conditional_Introduction.md +++ b/Logic/Proofs/Conditional_Introduction.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- -If we can show that $Q$ follows from $P$ (typically via a subproof) than we can assert that P implies Q. This is also sometimes known as _Conditional Proof_ +# Conditional Introduction -![cond-intro.png](../img/cond-intro.png) +If we can show that $Q$ follows from $P$ (typically via a sub-proof) than we can assert that P implies Q. This is also sometimes known as _Conditional Proof_ + +![](/_img/cond-intro.png) diff --git a/Logic/Proofs/Conjunction_Elimination.md b/Logic/Proofs/Conjunction_Elimination.md index 02ec5cf..e37a62f 100644 --- a/Logic/Proofs/Conjunction_Elimination.md +++ b/Logic/Proofs/Conjunction_Elimination.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- +# Conditional Elimination + If a conjunction exists, it means that both conjuncts are the case; therefore we can legitimately extract either one of them. Also known as _Simplification_. -![conjunc-elim.png](../img/conjunc-elim.png) +![](/_img/conjunc-elim.png) diff --git a/Logic/Proofs/Conjunction_Introduction.md b/Logic/Proofs/Conjunction_Introduction.md index 1f48a31..2aa6f55 100644 --- a/Logic/Proofs/Conjunction_Introduction.md +++ b/Logic/Proofs/Conjunction_Introduction.md @@ -1,9 +1,9 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- If two conjuncts have each been independently derived then they can be conjoined. Also known more simply as _Conjunction_ -![conjunc-intro.png](../img/conjunc-intro.png) +![](/_img/conjunc-intro.png) diff --git a/Logic/Proofs/Disjunction_Elimination.md b/Logic/Proofs/Disjunction_Elimination.md index abe8717..4abc0da 100644 --- a/Logic/Proofs/Disjunction_Elimination.md +++ b/Logic/Proofs/Disjunction_Elimination.md @@ -1,18 +1,20 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- +# Disjunction Elimination + This rule is sometimes also referred to as _Constructive Dilemma_. This can be a bit tricky to understand because the goal is to derive or _introduce_ a new proposition separate from the disjunction you start out with. This may be disjunction, a single proposition or a proposition containing any other logical connective. You do this by constructing two sub-proofs, one for each of the disjuncts comprising the disjunction you start out with. If you can derive your target proposition as the conclusion of each subproof then you may invoke the conclusion in the main proof and take it to be derived. -![disjunc-elim.png](../img/disjunc-elim.png) +![](/_img/disjunc-elim.png) _Here is an example where Disjunction Elimination is used to derive a new disjunction._ -![proofs-drawio-Page-6.drawio.png](../img/proofs-drawio-Page-6.drawio.png) +![](/_img/proofs-drawio-Page-6.drawio.png) _Here are two further examples that use Disjunction Elimination to derive singular propositions_ -![ORelim1.png](../img/ORelim1.png) -![ORelim2.png](../img/ORelim2.png) +![](/_img/ORelim1.png) +![](/_img/ORelim2.png) diff --git a/Logic/Proofs/Disjunction_Introduction.md b/Logic/Proofs/Disjunction_Introduction.md index d50e8b2..a9da165 100644 --- a/Logic/Proofs/Disjunction_Introduction.md +++ b/Logic/Proofs/Disjunction_Introduction.md @@ -1,10 +1,12 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- +# Disjunction Introduction + This rule can seem a little odd: like we are randomly introducing an additional proposition without giving any justification. However this is just a consequence of the fact if $P$ is true, so is $P \lor Q$ since disjunction is not the same as conjunction: only one disjunct needs to be true for the compound disjunction to be true. This is represented in the context of [truth-trees](Truth-trees.md#disjunction-decomposition) by the fact that truth can pass up via either branch of a disjunction pattern. This rule is sometimes also referred to (confusingly) as _Addition_. -![disjunc-intro.png](../img/disjunc-intro.png) +![](/_img/disjunc-intro.png) diff --git a/Logic/Proofs/Formal_proofs_in_propositional_logic.md b/Logic/Proofs/Formal_proofs_in_propositional_logic.md index 79c1be8..9c8728a 100644 --- a/Logic/Proofs/Formal_proofs_in_propositional_logic.md +++ b/Logic/Proofs/Formal_proofs_in_propositional_logic.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- +# Formal proofs in propositional logic + When we construct a formal proof in logic we are seeking to show that a certain proposition is **derivable** from other propositions. We use the words _derivation_ and _proof_ interchangeably. > A sentence $P$ is derivable in a system of propositional logic from a finite set of sentences if and only if there is a derivation in this system in which all and only the members of the set are **primary assumptions** and $P$ is the sentence on the last line. @@ -15,11 +17,12 @@ Derivability is therefore a property that a proposition can possess relative to For instance to demonstrate derivability for: $$ -{\sim F \lor D, F, D \supset (G & H)} \vdash G &H +\{ \lnot F \lor D, F, D \rightarrow (G \land H) \} \vdash G \land H $$ -We would establish $\sim F \lor D, F, D \supset (G & H)$ as primary assumptions and then, using the derivation rules of the system conclude with $G&H$. Every sentence in the derivation is either a **primary assumption** or an **auxiliary** assumption or justified by the rules of the derivation. An auxiliary assumption is one belonging to a sub-derivation. The primary assumptions belong to the main derivation. -For any given derivation of the form $\Gamma \vdash P$ there may be a number of ways of demonstrating the derivation (more than one application of the rules governing the system) but only one is sufficient to establish derivability. +We would establish $\lnot F \lor D, F, D \rightarrow (G \land H)$ as primary assumptions and then, using the derivation rules of the system conclude with $G\land H$. Every sentence in the derivation is either a **primary assumption** or an **auxiliary** assumption or justified by the rules of the derivation. + +An auxiliary assumption is an assumption belonging to a sub-derivation. Primary assumptions belong to the main derivation. For any given derivation of the form $\Gamma \vdash P$ there may be a number of ways of demonstrating the derivation (more than one application of the rules governing the system) but one alone is sufficient to establish derivability. > We will tend to use the terms _derivation_ and _proof_ interchangeably but we should note that there is a technical distinction in that a **proof is a derivation in which all of the assumptions have been discharged** @@ -29,13 +32,14 @@ We place assumptions above derivations and mark them _A_ in the right-hand margi We divide assumptions from derivations with a horizontal line. We number each line and use this to refer to the line we are applying the derivation to. Sub-proofs follow this structure recursively. This is known as _Fitch notation_ -_Schematically_ -![proofs-drawio-Page-5.drawio.png](../img/proofs-drawio-Page-5.drawio.png) +_Schematically_: -_Applied example_ +![](/_img/proofs-drawio-Page-5.drawio.png) -![proofs-drawio-Page-6.drawio.png](../img/proofs-drawio-Page-6.drawio.png) +_Applied example_: + +![](/_img/proofs-drawio-Page-6.drawio.png) ## Sub-proofs @@ -43,7 +47,7 @@ When a sub-proof is terminated, the assumption with which it starts is said to b ## Derivation rules -Derivation rules are [syntactic](Syntax%20of%20sentential%20logic.md) rather than semantic. They are applied on the basis of their form rather than on the basis of the truth conditions of the sentences they are applied to. +Derivation rules are [syntactic](/Logic/Propositional_logic/Syntax_of_sentential_logic.md) rather than semantic. They are applied on the basis of their form rather than on the basis of the truth conditions of the sentences they are applied to. > Derivation rules can be applied without having an interpretation of the symbols in mind. A derivation rule tells us that: given a group of symbols with a certain structure, we can write down another group of symbols with a certain structure. @@ -51,13 +55,13 @@ Each of the main logical connectives has an associated derivation rule. The bina The main derivation rules: -- [Negation Introduction](Negation%20Introduction.md) -- [Negation Elimination](Negation%20Elimination.md) -- [Conjunction Introduction](Conjunction%20Introduction.md) -- [Conjunction Elimination](Conjunction%20Elimination.md) -- [Disjunction Introduction](Disjunction%20Introduction.md) -- [Disjunction Elimination](Disjunction%20Elimination.md) -- [Conditional Introduction](Conditional%20Introduction.md) -- [Disjunction Elimination](Disjunction%20Elimination.md) -- [Biconditional Introduction](Biconditional%20Introduction.md) -- [Biconditional Elimination](Biconditional%20Elimination.md) +- [Negation Introduction](/Logic/Proofs/Negation_Introduction.md) +- [Negation Elimination](/Logic/Proofs/Negation_Elimination.md) +- [Conjunction Introduction](/Logic/Proofs/Conjunction_Introduction.md) +- [Conjunction Elimination](/Logic/Proofs/Conditional_Elimination.md) +- [Disjunction Introduction](/Logic/Proofs/Disjunction_Introduction.md) +- [Disjunction Elimination](/Logic/Proofs/Disjunction_Elimination.md) +- [Conditional Introduction](/Logic/Proofs/Conditional_Introduction.md) +- [Disjunction Elimination](/Logic/Proofs/Disjunction_Elimination.md) +- [Biconditional Introduction](/Logic/Proofs/Biconditional_Introduction.md) +- [Biconditional Elimination](/Logic/Proofs/Biconditional_Elimination.md) diff --git a/Logic/Proofs/Negation_Elimination.md b/Logic/Proofs/Negation_Elimination.md index f61c8c6..c14602a 100644 --- a/Logic/Proofs/Negation_Elimination.md +++ b/Logic/Proofs/Negation_Elimination.md @@ -1,8 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- -![negate-elim 1.png](../img/negate-elim%201.png) -Like the [introduction](Negation%20Elimination.md) rule for negation, the elimination rule also works by deriving a contradiction. It is basically _Negation Introduction_ in reverse. Instead of starting the subproof with a true proposition from which you derive a contradiction, you start with the negation of a proposition, derive a contradiction and then assert the positive of the negated proposition you started out with. +# Negation Elimination + +Like the [introduction](/Logic/Proofs/Negation_Introduction.md) rule for negation, the elimination rule also works by deriving a contradiction. It is basically _Negation Introduction_ in reverse. Instead of starting the sub-proof with a true proposition from which you derive a contradiction, you start with the negation of a proposition, derive a contradiction and then assert the positive of the negated proposition you started out with. + +![](/_img/negate-elim.png) diff --git a/Logic/Proofs/Negation_Introduction.md b/Logic/Proofs/Negation_Introduction.md index 1e48737..fef95e3 100644 --- a/Logic/Proofs/Negation_Introduction.md +++ b/Logic/Proofs/Negation_Introduction.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- -This is also known as _proof by contradiction_. You start with an assumption declared in a subproof. If you can derive a contradiction from this assumption (typically from the introduction of another proposition and its negation), then you are permitted to derive the negation of the auxiliary assumption in the main proof. +# Negation Introduction -[]()![negate-intro 1.png](../img/negate-intro%201.png) +This is also known as _proof by contradiction_. You start with an assumption declared in a sub-proof. If you can derive a contradiction from this assumption (typically from the introduction of another proposition and its negation), then you are permitted to derive the negation of the auxiliary assumption in the main proof. + +![](/_img/negate-intro.png) diff --git a/Logic/Proofs/Reiteration.md b/Logic/Proofs/Reiteration.md index bdf7c50..e0e8c6f 100644 --- a/Logic/Proofs/Reiteration.md +++ b/Logic/Proofs/Reiteration.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [derivation-rules] --- -**Reiteration (R)** allows us to restate any proposition already in the proof within the main proof or a more deeply nested subproof. Reiteration allows us to reuse any assumptions, or propositions derived from assumptions, without having to introduce a new dependency with another assumption. +# Reiteration -![reiteration.png](../img/reiteration.png) +**Reiteration (R)** allows us to restate any proposition already in the proof within the main proof or a more deeply nested sub-proof. Reiteration allows us to reuse any assumptions, or propositions derived from assumptions, without having to introduce a new dependency with another assumption. + +![](/_img/reiteration.png) diff --git a/Logic/Proofs/Strategies_for_constructing_proofs.md b/Logic/Proofs/Strategies_for_constructing_proofs.md index e8f66b8..ab741e4 100644 --- a/Logic/Proofs/Strategies_for_constructing_proofs.md +++ b/Logic/Proofs/Strategies_for_constructing_proofs.md @@ -1,9 +1,11 @@ --- categories: - - Mathematics -tags: [logic, proofs] + - Logic +tags: [propositional-logic] --- +# Strategies for constructing proofs in propositional logic + ## General strategy - Break complex propositions into simpler sentences by using the elimination rules @@ -13,80 +15,83 @@ tags: [logic, proofs] The approach above describes the general form of a proof but of course it will not always work and there will be cases where the route to the desired derivation is more circuitous. In these instances it is to best to combine this general top level strategy with goal analysis. -Goal analysis is a [recursive](../Algorithms%20&%20Data%20Structures/Recursion.md) strategy which proceeds by using a 'goal' proposition to guide the construction of intermediary derivations. +Goal analysis is a [recursive](/Data_Structures/Recursion.md) strategy which proceeds by using a 'goal' proposition to guide the construction of intermediary derivations. -Assume that we want to show that an argument is [valid](Validity%20and%20entailment.md#validity). Then our ultimate goal is to derive the conclusion from the premises we are given. We first ask ourselves: _which propositions if we could derive them, would allow us to easily derive the conclusion_? (For example, these propositions might be two simple propositions that when combined with [Conjunction Introduction](Conjunction%20Introduction.md) give us the conclusion.) Deriving these propositions then becomes the new intermediate goal. +Assume that we want to show that an argument is [valid](/Logic/General_concepts/Validity_and_entailment.md#validity). Then our ultimate goal is to derive the conclusion from the premises we are given. We first ask ourselves: _which propositions if we could derive them, would allow us to easily derive the conclusion_? (For example, these propositions might be two simple propositions that when combined with [Conjunction Introduction](/Logic/Proofs/Conjunction_Introduction.md) give us the conclusion.) Deriving these propositions then becomes the new intermediate goal. If arriving at these propositions is not trivial, we then ask ourselves the question again: _which propositions would permit us to derive the intermediary propositions we need_? You keep working back in this manner until you reach a base level. Then it is just a matter or working upwards from each set of derived intermediary propositions until you reach the ultimate goal. ### Demonstration -Let's say we want to prove $(L \lor A) & D$ from the propositions $\sim N$ and $(\sim N \supset L) & (D \equiv \sim N)$. +Let's say we want to prove $(L \lor A) \land D$ from the propositions $\lnot N$ and $((\lnot N \rightarrow L) \land (D \leftrightarrow \lnot N))$. -First, we consider what is the easiest possible way of achieving the proposition $(L \lor A) & D$. Clearly it is to separately derive each disjunct ($L \lor A$ and $D$) and then combine them with [Conjunction Introduction](Conjunction%20Introduction.md). This provides us with our first goal: to derive each of the separate conjuncts. +First, we consider what is the easiest possible way of achieving the proposition $(L \lor A) \land D$. Clearly it is to separately derive each disjunct ($L \lor A$ and $D$) and then combine them with [Conjunction Introduction](/Logic/Proofs/Conditional_Introduction.md). This provides us with our first goal: to derive each of the separate conjuncts. -Let's start with $D$: where does it occur in the assumptions? It occurs in the compound $(\sim N \supset L) & (D \equiv \sim N)$, but only in the first conjunct. We can get this simply bu applying [Conjunction Elimination](Conjunction%20Elimination.md). +Let's start with $D$: where does it occur in the assumptions? It occurs in the compound $(\lnot N \rightarrow L) \land (D \leftrightarrow \lnot N)$, but only in the first conjunct. We can get this simply but applying [Conjunction Elimination](Conjunction%20Elimination.md). So far we have: -![step1.png](../img/step1.png) +![](/_img/step1.png) -Now we just need to get $D$ from the proposition at line 3. This is easy since we already have access to the consequent of the biconditional at line 1. Therefore we can apply [Biconditional Elimination](Biconditional%20Elimination.md) at line 3 to get $D$. We are now halfway there: +Now we just need to get $D$ from the proposition at line 3. This is easy since we already have access to the consequent of the biconditional at line 1. Therefore we can apply [Biconditional Elimination](/Logic/Proofs/Biconditional_Elimination.md)) at line 3 to get $D$. We are now halfway there: -![step2.png](../img/step2.png) +![](/_img/step2.png) -Next we need to turn our attention to deriving $L \lor A$. How can we obtain $L$ ? Well it is contained within the first conjunct of the assumption on line 2. Again, we can get this through the application of [Conjunction Elimination](Conjunction%20Elimination.md). -Now, how do we get $L$ from $(\sim N \supset L)$? Well, we already have the antecedent $\sim N$ as an assumption on the first line, so we can use [Conditional Elimination](Conditional%20Elimination.md) to derive $L$. These two steps give us: +Next we need to turn our attention to deriving $L \lor A$. How can we obtain $L$ ? Well it is contained within the first conjunct of the assumption on line 2. Again, we can get this through the application of [Conjunction Elimination](/Logic/Proofs/Conjunction_Elimination.md). +Now, how do we get $L$ from $(\lnot N \rightarrow L)$? Well, we already have the antecedent $\lnot N$ as an assumption on the first line, so we can use [Conditional Elimination](/Logic/Proofs/Conditional_Elimination.md) to derive $L$. These two steps give us: -![step3.png](../img/step3.png) +![](/_img/step3.png) -Now we need to get from $L$ to $L \lor A$. This is really straightforward because by using [Disjunction Introduction](Disjunction%20Introduction.md) we can get from any sentence to a disjunction. Finally, having assembled all the constituent parts of the conjunction that is the conclusion, we can combine them with [Conjunction Introduction](Conjunction%20Introduction.md) as we had planned at the outset. +Now we need to get from $L$ to $L \lor A$. This is really straightforward because by using [Disjunction Introduction](/Logic/Proofs/Disjunction_Introduction.md)) we can get from any sentence to a disjunction. Finally, having assembled all the constituent parts of the conjunction that is the conclusion, we can combine them with [Conjunction Introduction](/Logic/Proofs/Conjunction_Introduction.md) as we had planned at the outset. -![step4.png](../img/step4.png) +![](/_img/step4.png) ### A further example We will seek to prove the following: $$ -{ \sim L \equiv \[X & (\sim S \lor B)\], (E & C) \supset \sim L, (E & R) & C} \vdash X & (\sim S \lor B) +\{ \lnot L \leftrightarrow [X \land (\lnot S \lor B) ], (E \land C) \rightarrow \lnot L, (E \land R) \land C \} \vdash X \land (\lnot S \lor B) $$ -The requirements here could easily mislead us. We see that the target proposition is a conjunction so we might think that the best strategy is to seek to derive each conjunct and then combine them via [Conjunction Introduction](Conjunction%20Introduction.md). +The requirements here could easily mislead us. We see that the target proposition is a conjunction so we might think that the best strategy is to seek to derive each conjunct and then combine them via [Conjunction Introduction](/Logic/Proofs/Conjunction_Introduction.md)). -Actually, if we look more closely, there is a better approach. The target proposition is contained in the first premise as the consequent to the biconditional ($\sim L \equiv \[X & (\sim S \lor B)\]$). A better approach is therefore to seek to derive the antecedent ($\sim L$) and then use [Biconditional Elimination](Biconditional%20Elimination.md) to extract the target sentence which is the consequent. +Actually, if we look more closely, there is a better approach. The target proposition is contained in the first premise as the consequent to the biconditional ($\lnot L \leftrightarrow [X \land (\lnot S \lor B)]$). A better approach is therefore to seek to derive the antecedent ($\lnot L$) and then use [Biconditional Elimination](/Logic/Proofs/Biconditional_Elimination.md) to extract the target sentence which is the consequent. -![proof.png](../img/proof.png) +![proof.png](/_img/proof.png) ## Proving theorems -When we are proving [theorems](Theorems%20and%20empty%20sets.md) we do not have a set of assumptions to work from when constructing the proof. We must derive the target sentence from the 'empty set' which is the target sentence itself. It is therefore like a process of reverse engineering. +When we are proving [theorems](/Logic/Laws_and_theorems.md/Theorems_and_empty_sets.md#theorems-and-empty-sets) we do not have a set of assumptions to work from when constructing the proof. We must derive the target sentence from the 'empty set' which is the target sentence itself. It is therefore like a process of reverse engineering. ### Demonstration -\_Prove \_ $\vdash (U & Y) \supset \[L \supset (U & L)\]$ +_Prove:_ $\vdash (U \land Y) \rightarrow [L \rightarrow (U \land L)]$ -Our strategy here is to identify the main connective in the proposition we want to derive (the [material conditional](Truth-functional%20connectives.md#material-conditional-a-k-a-implication)). We then assume the antecedent and attempt to derive the consequent from it. +Our strategy here is to identify the main connective in the proposition we want to derive (the material conditional). We then assume the antecedent and attempt to derive the consequent from it. -![proofs-drawio-Page-5.drawio 4.png](../img/proofs-drawio-Page-5.drawio%204.png) +![](/_img/theoremproof.png) ## A complex theorem proof -_Prove_ $\vdash (\sim A \lor \sim B) \equiv \sim(A & B)$ +_Prove_ $\vdash (\lnot A \lor \lnot B) \leftrightarrow \lnot(A \land B)$ -![dsfdsfsdfwe.png](../img/dsfdsfsdfwe.png) +![](/_img/dsfdsfsdfwe.png) ### Walkthrough **Lines 1-12** -- Our auxiliary goal is to prove $\sim (A \lor B) \supset \sim (A & B)$. -- Our starting assumption is to a disjunction. Thus we can apply [Disjunction Elimination](Disjunction%20Elimination.md) to show that our goal sentence $\sim(A & B)$ follows from each of the disjuncts ($\sim A$ and $\sim B$) in dedicated subproofs. If we can do this, we have the right to derive $\sim (A & B$). -- In both cases($\sim A \vdash \sim (A & B$) and ($\sim B \vdash \sim (A & B$) we require another subproof to reach the target as there is no easy path available. So we derive a negation from $A & B$ so that we can negate it as $\sim (A & B$). -- Having done this, we can discharge the [Disjunction Elimination](Disjunction%20Elimination.md) subproofs and derive $\sim (A & B$) from $\sim A \lor \sim B$ +- Our auxiliary goal is to prove $\lnot (A \lor B) \rightarrow \lnot (A \land B)$. + +- Our starting assumption is to a disjunction. Thus we can apply [Disjunction Elimination](/Logic/Proofs/Disjunction_Elimination.md) to show that our goal sentence $\lnot(A \land B)$ follows from each of the disjuncts ($\lnot A$ and $\lnot B$) in dedicated sub-proofs. If we can do this, we have the right to derive $\lnot (A \land B)$. + +- In both cases($\lnot A \vdash \lnot (A \land B)$) and ($\lnot B \vdash \lnot (A \land B)$ we require another sub-proof to reach the target as there is no easy path available. So we derive a negation from $A \land B$ so that we can negate it as $\lnot (A \land B)$. + +- Having done this, we can discharge the [Disjunction Elimination](/Logic/Proofs/Disjunction_Elimination.md) sub-proofs and derive $\lnot (A \land B)$ from $\lnot A \lor \lnot B$ **Lines 13-26** -- Our auxiliary goal is to prove $\sim (A & B) \supset \sim A \lor \sim B$. This will require a different approach to the above because we are not working from a disjunction anymore, we have a negated conjunction. -- We will do this by assuming the negation of what we want to prove ($\sim (\sim A \lor \sim B)$) and then apply [Negation Elimination](Negation%20Elimination.md) to get $\sim A \lor \sim B$. -- This requires us to derive a contradiction. We get this on lines 23 and 24. This requires as previous steps that we have two subproofs that use [Negation Elimination](Negation%20Elimination.md) to release $A$ and $B$ +- Our auxiliary goal is to prove $\lnot (A \land B) \rightarrow \lnot A \lor \lnot B$. This will require a different approach to the above because we are not working from a disjunction anymore, we have a negated conjunction. +- We will do this by assuming the negation of what we want to prove ($\lnot (\lnot A \lor \lnot B)$) and then apply [Negation Elimination](/Logic/Proofs/Negation_Elimination.md) to get $\lnot A \lor \lnot B$. +- This requires us to derive a contradiction. We get this on lines 23 and 24. This requires as previous steps that we have two sub-proofs that use [Negation Elimination](/Logic/Proofs/Negation_Elimination.md) to release $A$ and $B$ diff --git a/Logic/Propositional_logic/Atomic_and_molecular_propositions.md b/Logic/Propositional_logic/Atomic_and_molecular_propositions.md new file mode 100644 index 0000000..2dc5840 --- /dev/null +++ b/Logic/Propositional_logic/Atomic_and_molecular_propositions.md @@ -0,0 +1,53 @@ +--- +categories: + - Logic +tags: [propositional-logic] +--- + +# Atomic and molecular propositions + +Propositions are expressions **that have truth values**, either true or false. + +We call a proposition which does not contain a logical connective (or 'sentential connective') a **simple proposition**. + +We call a proposition that does contain a logical connective, a **compound proposition**. + +Simple propositions are represented within a formal language of sentential logic with a single character, customarily _P_ or _Q_. When we refer to the formal representation of such propositions in our system of sentential logic (SL) we call them **atomic propositions**. + +Compound propositions consist in single characters for each atomic proposition that they comprise, combined with a symbol for the logical connective. When we refer to the formal representation of such propositions in SL we call them **molecular propositions**. + +### Demonstration + +Atomic proposition: + +``` +Socrates was a philosopher. +(P) +``` + +Molecular proposition: + +``` +Socrates was a philosopher and a drinker. +(P & Q) +``` + +Connectives in natural language often obscure the logical basis of the proposition being expressed (where such a proposition contains a proposition, i.e. excluding propositions that are _logically indeterminate_. The molecular proposition is above is such an example. In this instance the proposition can be expressed more precisely as: + +``` +Socrates was a philosopher and Socrates was a drinker. +``` + +Where propositions in natural language cannot be elucidated by the addition of implied logical connectives in the manner above, they must be treated not as molecular propositions but as atomic proposition. Example: + +``` +Two splashes of gin and a few drops of vermouth make a great martini. +``` + +If we were to formalise this as: + +``` +Two splashes of gin make a great martini and a few drops of vermouth make a great martini. +``` + +We would lose the sense of the original and we would not be uncovering any logic that is in the original. diff --git a/Logic/Propositional_logic/Atomic_and_molecular_sentences.md b/Logic/Propositional_logic/Atomic_and_molecular_sentences.md deleted file mode 100644 index b0c59e5..0000000 --- a/Logic/Propositional_logic/Atomic_and_molecular_sentences.md +++ /dev/null @@ -1,51 +0,0 @@ ---- -categories: - - Mathematics -tags: [logic] ---- - -Sentences or propositions (we will use 'sentences' for consistency) are expressions **that have truth values**, either true or false. - -We call a sentence which does not contain a logical connective (or 'sentential connective') a **simple sentence**. - -We call a sentence that does contain a logical connective, a **compound sentence**. - -Simple sentences are represented within a formal language of sentential logic with a single character, customarily _P_ or _Q_. When we refer to the formal representation of such sentences in our system of sentential logic (SL) we call them **atomic sentences**. - -Compound sentences consist in single characters for each atomic sentence that they comprise, combined with a symbol for the logical connective. When we refer to the formal representation of such sentences in SL we call them **molecular sentences**. - -### Demonstration - -Atomic sentence: - -``` -Socrates was a philosopher. -(P) -``` - -Molecular sentence: - -``` -Socrates was a philosopher and a drinker. -(P & Q) -``` - -Connectives in natural language often obscure the logical basis of the proposition being expressed (where such a sentence contains a proposition, i.e. excluding sentences that are _logically indeterminate_. The molecular sentence is above is such an example. In this instance the sentence can be expressed more precisely as: - -``` -Socrates was a philosopher and Socrates was a drinker. -``` - -Where sentences in natural language cannot be elucidated by the addition of implied logical connectives in the manner above, they must be treated not as molecular sentences but as atomic sentence. Example: - -``` -Two splashes of gin and a few drops of vermouth make a great martini. -``` - -If we were to formalise this as: - -``` -Two splashes of gin make a great martini and a few drops of vermouth make a great martini. -``` - -We would lose the sense of the original and we would not be uncovering any logic that is in the original. diff --git a/Logic/Propositional_logic/Boolean_algebra.md b/Logic/Propositional_logic/Boolean_algebra.md index 8125cc6..41e83db 100644 --- a/Logic/Propositional_logic/Boolean_algebra.md +++ b/Logic/Propositional_logic/Boolean_algebra.md @@ -2,7 +2,7 @@ categories: - Logic - Computer Architecture -tags: [propositional-logic, algebra] +tags: [propositional-logic, algebra, nand-to-tetris] --- # Boolean algebra @@ -89,7 +89,7 @@ $$ We can employ DeMorgan's Laws to convert the second conjunct to a different form: $$ - \lnot (x \lor x) = \lnot x \land \lnot y + \lnot (x \lor y) = \lnot x \land \lnot y $$ So now we have: diff --git a/Logic/Propositional_logic/Boolean_function_synthesis.md b/Logic/Propositional_logic/Boolean_function_synthesis.md index dab9bf3..ca8a11d 100644 --- a/Logic/Propositional_logic/Boolean_function_synthesis.md +++ b/Logic/Propositional_logic/Boolean_function_synthesis.md @@ -7,9 +7,11 @@ tags: [logic, propositional-logic, nand-to-tetris] # Boolean function synthesis -When we looked at [boolean functions](/Logic/Propositional_logic/Boolean_functions.md) we were working in a particular direction: from a function to a truth table. When we do Boolean function synthesis we work in the opposite direction: from a function to a truth table. +When we looked at [boolean functions](/Logic/Propositional_logic/Boolean_functions.md) we were working in a particular direction: from a function to a truth table. When we do Boolean function synthesis we work in the opposite direction: from a truth table to a function. -This is an important skill that we will use when constructing [logic circuits](/Electronics_and_Hardware/Digital_circuits/Digital_circuits.md). We will go from truth conditions (i.e. what we want the circuit to do and when we want it to do it) to a function expression which is then reduced and implemented with [logic gates](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md). +This is an important skill that we will use when constructing [logic circuits](/Electronics_and_Hardware/Digital_circuits/Digital_circuits.md). We will go from truth conditions (i.e. what we want the circuit to do and when we want it to do it) to a function expression which is then reduced to its simplest form and implemented with [logic gates](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md). Specifically, NAND gates. + +We will show here that a complex logical expression can be reduced to an equivalent expression that uses only the NAND operator. ## The process @@ -27,7 +29,7 @@ Let's say we have the following truth table: | Line | $x$ | $y$ | $z$ | $f$ | | ---- | --- | --- | --- | --- | -| 1 | 0 | 0 | 0 | 1 | +| 1 | 0 | 0 | 0 | 0 | | 2 | 0 | 0 | 1 | 0 | | 3 | 0 | 1 | 0 | 1 | | 4 | 0 | 1 | 1 | 0 | @@ -46,16 +48,16 @@ We only need to focus on lines 1, 3, and 5 since they have the output 1: For each line we construct a Boolean expression that would result in the value in the $f$ column. In other words we construct the function: -| Line | $x$ | $y$ | $z$ | $f$ | -| ---- | --- | --- | --- | ------------------------------------------- | -| 1 | 0 | 0 | 0 | $ \lnot(x) \land \lnot (y) \land \lnot(z) $ | -| 3 | 0 | 1 | 0 | $ \lnot(x) \land y \land \lnot(z) $ | -| 5 | 1 | 0 | 0 | $ x \land \lnot(y) \land \lnot(z) $ | +| Line | $x$ | $y$ | $z$ | $f$ | +| ---- | --- | --- | --- | ----------------------------------------- | +| 1 | 0 | 0 | 0 | $\lnot(x) \land \lnot (y) \land \lnot(z)$ | +| 3 | 0 | 1 | 0 | $\lnot(x) \land y \land \lnot(z)$ | +| 5 | 1 | 0 | 0 | $x \land \lnot(y) \land \lnot(z)$ | -We can now join each expression to create a complex expression that covers the entire truth table. Since 1 will be output for any one of these sub-expressions we can just join them up with OR: +We can now join each expression to create a complex expression that covers the entire truth table using OR: $$ -(\lnot(x) \land \lnot (y) \land \lnot(z)) \lor (\lnot(x) \land y \land \lnot(z)) \lor (x \land \lnot(y) \land \lnot(z)) +(\lnot(x) \land \lnot (y) \land \lnot(z)) \\ \lor \\ (\lnot(x) \land y \land \lnot(z)) \\ \lor \\ (x \land \lnot(y) \land \lnot(z)) $$ It's clear that we have transcribed the truth conditions accurately but that we are doing so in a rather verbose way. We can simplify by just looking at the position of the 1s in the truth table. Notice: @@ -69,16 +71,43 @@ $$ (\lnot(x) \land \lnot(z)) \lor (\lnot(y) \land \lnot(z)) $$ -Notice that $\lnot(z)$ is repeated so we can remove the repetition: +Notice that $\lnot(z)$ is repeated so we can remove the repetition through [idempotence](/Logic/Propositional_logic/Boolean_algebra.md#idempotent-law): $$ \lnot z \land (\lnot(x) \lor \lnot(y)) $$ -The upshot is that we now have a simpler expression that uses only NOT, OR and AND. We could therefore construct a circuit that just uses these gates to construct the conditions we specified in the first truth table. +The upshot is that we now have a simpler expression that uses only NOT, OR and AND. These are the fundamental logic gates thus we are able to construct a circuit that embodies the logic of the expression. > This is important and is an instance of the general theorem that _any Boolean function_ can be represented using an expression containing AND, OR and NOT operations -But even this is too complex. We could get rid of the OR and just use AND and NOT, in other words, NAND: +But even this is too complex. We could get rid of the OR and just use AND and NOT: -stopped at 6:38 +We can prove this theorem by showing that an expression with AND, NOT, and OR can be formulated as an equivalent expression using just NOT and AND: + +$$ + x \lor y = \lnot(\lnot(x) \land \lnot(y)) +$$ + +| $x$ | $y$ | $x \lor y$ | $\lnot(\lnot(x) \land \lnot(y)$ | +| --- | --- | ---------- | ------------------------------- | +| 0 | 0 | 0 | 0 | +| 0 | 1 | 1 | 1 | +| 1 | 0 | 1 | 1 | +| 1 | 1 | 1 | 1 | + +Finally, we can simplify even further by doing away with AND and NOT and using a single [NAND gate](/Electronics_and_Hardware/Digital_circuits/Logic_gates.md#nand-gate) which embodies the logic of both, being true in all instances where AND would be false: $\lnot (x \land y)$. + +Let's prove the theorem that every logical expression can be formulated as a NAND function. To do this we need to show that both NOT and AND can be converted to NAND. + +NOT: + +$$ + \lnot(x) = x \lnot\land x +$$ + +AND: + +$$ + x \land y = \lnot(x \lnot\land y) +$$ diff --git a/Logic/Propositional_logic/Boolean_functions.md b/Logic/Propositional_logic/Boolean_functions.md index b649e80..b7ee6f1 100644 --- a/Logic/Propositional_logic/Boolean_functions.md +++ b/Logic/Propositional_logic/Boolean_functions.md @@ -15,11 +15,11 @@ $$ Here is a work through where $f(1, 0, 1)$: -- The first disjunction : $ \lnot(x) \land z $ is false because $x$ is 1 and $z$ is 0 +- The first disjunction : $\lnot(x) \land z$ is false because $x$ is 1 and $z$ is 0 - The second disjunction: $x \land y$ is false because $x$ is 1 and $y$ is 1 - The overall function returns false because the main connective is disjunction and both of its disjuncts are false -We can compute all possible outputs of the function by constructing a [truth-table](/Logic/Propositional_logic/Truth-tables.md) with each possible variable as the truth conditions and the output of the function as the truth value: +We can compute all possible outputs of the function by constructing a [truth table](/Logic/Propositional_logic/Truth-tables.md) with each possible variable as the truth conditions and the output of the function as the truth value: | $x$ | $y$ | $z$ | $f(x,y,z) = (x \land y) \lor (\lnot(x) \land z )$ | | --- | --- | --- | ------------------------------------------------- | diff --git a/Logic/Propositional_logic/Syntax_of_propositional_logic.md b/Logic/Propositional_logic/Syntax_of_propositional_logic.md new file mode 100644 index 0000000..cb42e31 --- /dev/null +++ b/Logic/Propositional_logic/Syntax_of_propositional_logic.md @@ -0,0 +1,66 @@ +--- +categories: + - Logic +tags: [propositional-logic] +--- + +# Syntax of propositional logic + +## Syntax of formal languages versus semantics + +> The syntactical study of a language is the study of the expressions of the language and the relations among them _without regard_ to the possible interpretations or 'meaning' of these expressions. + +Syntax is talking about the order and placement of propositions relative to connectives and what constitutes a well-formed expression in these terms. Semantics is about what the connectives mean, in other words: truth-functions and truth-values and not just placement and order. + +## Formal specification of the syntax of the language of Sentential Logic + +### Vocabulary + +Propositions in SL are capitalised Roman letters (non-bold) with or without natural number subscripts. We may call these proposition letters. For example: + +$$ + P, Q, R,... P_{1}, Q_{1}, R_{1}, ... +$$ + +The connectives of SL are the five truth-functional connectives: + +$$ + \lnot, \land, \lor, \rightarrow, \leftrightarrow +$$ + +The punctuation marks of SL consist in the left and right parentheses: + +$$ + ( ) +$$ + +### Grammar + +1. Every letter in a statement is a proposition. +2. If $P$ is a proposition then $\lnot P$ is a proposition. +3. If $P$ and $Q$ are propositions, then $P \land Q$ is a proposition +4. If $P$ and $Q$ are propositions, then $P \lor Q$ is a proposition +5. If $P$ and $Q$ are propositions, then $P \rightarrow Q$ is a proposition +6. If $P$ and $Q$ are propositions, then $P \leftrightarrow Q$ is a proposition +7. Nothing is a proposition unless it can be formed by repeated application of rules 1-6 + +### Additional syntactic concepts + +We also distinguish: + +- the **main connective** +- **immediate sentential components** +- **sentential components** +- **atomic components** + +These definitions provide a formal specification of the concepts of [atomic and molecular propositions](/Logic/Propositional_logic/Atomic_and_molecular_propositions.md) introduced previously. + +1. If $P$ is an atomic proposition, $P$ contains no connectives and hence does not have a main connective. $P$ has no immediate propositional components. +1. If $P$ is of the form $\lnot Q$ where $Q$ is a proposition, then the main connective of $P$ is the negation symbol that occurs before $Q$ and $Q$ is the immediate propositional component of $P$ +1. If P is of the form: + 1. $Q \land R$ + 1. $Q \lor R$ + 1. $Q \rightarrow R$ + 1. $Q \leftrightarrow R$ + +where $Q$ and $R$ are propositions, then the main connective of $P$ is the connective that occurs between $Q$ and $R$ and $Q$ and $R$ are the immediate propositional components of $P$. diff --git a/Logic/Propositional_logic/Syntax_of_sentential_logic.md b/Logic/Propositional_logic/Syntax_of_sentential_logic.md deleted file mode 100644 index d26a7c0..0000000 --- a/Logic/Propositional_logic/Syntax_of_sentential_logic.md +++ /dev/null @@ -1,64 +0,0 @@ ---- -categories: - - Mathematics -tags: [logic] ---- - -## Syntax of formal languages versus semantics - -> The syntactical study of a language is the study of the expressions of the language and the relations among them _without regard_ to the possible interpretations or 'meaning' of these expressions. - -Syntax is talking about the order and placement of propositions relative to connectives and what constitutes a well-formed expression in these terms. Semantics is about what the connectives mean, in other words: truth-functions and truth-values and not just placement and order. - -## Formal specification of the syntax of the language of Sentential Logic - -### Vocabulary - -Sentences in SL are capitalised Roman letters (non-bold) with or without natural number subscripts. We may call these sentence letters. For example: - -```plain -P, Q, R...P1, Q1, R1... -``` - -The connectives of SL are the five truth-functional connectives: - -``` -~, &, v, ⊃, ≡ -``` - -The punctuation marks of SL consist in the left and right parentheses: - -``` -( ) -``` - -### Grammar - -1. Every sentence letter is a sentence. -1. If **P** is a sentence then **~P** is a sentence. -1. If **P** and **Q** are sentences, then **(P & Q)** is a sentence -1. If **P** and **Q** are sentences, then **(P v Q)** is a sentence -1. If **P** and **Q** are sentences, then **(P ⊃ Q)** is a sentence -1. If **P** and **Q** are sentences, then **(P ≡ Q)** is a sentence -1. Nothing is a sentence unless it can be formed by repeated application of clauses 1-6 - -### Additional syntactic concepts - -We also distinguish: - -- the **main connective** -- **immediate sentential components** -- **sentential components** -- **atomic components** - -These definitions provide a formal specification of the concepts of atomic and molecular sentences _introduced earlier_. - -1. If **P** is an atomic sentence, **P** contains no connectives and hence does not have a main connective. **P** has no immediate sentential components. -1. If **P** is of the form **~Q** where **Q** is a sentence, then the main connective of **P** is the tilde that occurs before **Q** and **Q** is the immediate sentential component of **P**. -1. If P is of the form: - 1. **Q & R** - 1. **Q v R** - 1. **Q ⊃ R** - 1. **Q ≡ R** - -where **Q** and **R** are sentences, then the main connective of **P** is the connective that occurs between **Q** and **R** and **Q** and **R** are the immediate sentential components of **P**. diff --git a/Logic/Propositional_logic/Truth-functional_connectives.md b/Logic/Propositional_logic/Truth-functional_connectives.md index 0f4c7b3..adee96e 100644 --- a/Logic/Propositional_logic/Truth-functional_connectives.md +++ b/Logic/Propositional_logic/Truth-functional_connectives.md @@ -1,26 +1,26 @@ --- categories: - - Mathematics -tags: [logic] + - Logic +tags: [propositional-logic] --- -## Truth-functional connectives +# Truth-functional connectives -Sentences generated from other (simple) sentences by means of sentential connectives are [compound sentences](Atomic%20and%20molecular%20sentences.md). +Propositions generated from other (simple) propositions by means of propositional connectives are [compound propositions](/Logic/Propositional_logic/Atomic_and_molecular_propositions.md). -We know that logically determinant sentences express a truth value. When simple sentences are joined with a connective to make a compound sentence they also have a truth value. This is determined by the nature of the connective and the truth value of the constituent sentences. We therefore call connectives of this nature truth _functional_ connectives since the **truth value of the compound is a function of the truth values of its components**. +We know that [logically determinant](/Logic/General_concepts/Logical_indeterminacy.md) propositions express a truth value. When simple propositions are joined with a connective to make a compound proposition they also have a truth value. This is determined by the nature of the connective and the truth value of the constituent propositions. We therefore call connectives of this nature truth _functional_ connectives since the **truth value of the compound is a function of the truth values of its components**. -> A sentential connective is used truth-functionally if and only if it is used to generate a compound sentence from one or more sentences in such a way that the truth value of the generated compound is wholly determined by the truth-values of those one or more sentences from which the compound is generated, no matter what the truth values may be. +> A propositional connective is used truth-functionally if and only if it is used to generate a compound proposition from one or more propositions in such a way that the truth value of the generated compound is wholly determined by the truth-values of those one or more propositions from which the compound is generated, no matter what the truth values may be. -Each truth-functional connective has a characteristic **truth-table**. This discloses the conditions under which the constituent sentences have a given truth value when combined with one or more connectives. +Each truth-functional connective has a characteristic **truth table**. This discloses the conditions under which the constituent propositions have a given truth value when combined with one or more connectives. We shall now review each of the truth-functional connectives in detail. ### Conjunction -Conjunction is equivalent to the word AND in natural language. We use `&` as the symbol for this connective. +Conjunction is equivalent to the word AND in natural language. We use $\land$ as the symbol for this connective. -A molecular sentence joining two conjuncts P and Q is true iff both conjuncts are true and false otherwise: +A molecular proposition joining two conjuncts P and Q is true iff both conjuncts are true and false otherwise: ``` P Q P & Q @@ -34,7 +34,7 @@ F F F Conjunction is equivalent to the word OR in natural language. We use `v` as the symbol of this connective. -A molecular sentence joining two disjuncts P and Q is true if either disjunct is true or if both disjuncts are true and false otherwise. This corresponds to the inclusive sense of OR in natural language. +A molecular proposition joining two disjuncts P and Q is true if either disjunct is true or if both disjuncts are true and false otherwise. This corresponds to the inclusive sense of OR in natural language. ``` P Q P ∨ Q @@ -46,7 +46,7 @@ F F F ### Negation -In contrast to the two previous connectives, negation is a unary connective not a binary connective. We use `~` to symbolise negation. It does not join two or more sentences, it applies to one sentence as a whole. This can be a simple sentence or a complex sentence. It simply negates the truth-value of whichever sentence it is applied to. Hence applied to P, it is true if P is false. And if P is false, it is true when P is true. ! +In contrast to the two previous connectives, negation is a unary connective not a binary connective. We use `~` to symbolise negation. It does not join two or more propositions, it applies to one proposition as a whole. This can be a simple proposition or a complex proposition. It simply negates the truth-value of whichever proposition it is applied to. Hence applied to P, it is true if P is false. And if P is false, it is true when P is true. ! ``` P ~ P @@ -62,7 +62,7 @@ The material conditional approximates the meaning expressed in natural language If it rains today the pavement will be wet. ``` -We call the proposition that expresses the 'if' sentence the **antecedent** and the proposition that expresses the 'then' statement the **consequent**. The symbol we use to represent the material conditional is `⊃` although you may see `→` used as well. +We call the proposition that expresses the 'if' proposition the **antecedent** and the proposition that expresses the 'then' statement the **consequent**. The symbol we use to represent the material conditional is `⊃` although you may see `→` used as well. The truth table is as follows: @@ -74,7 +74,7 @@ F T T F F T ``` -The material conditional is perhaps the least intuitive of the logical connectives. The first case (TT) closely matches what we expect the connective to mean: it has rained so the pavement is wet. The antecedent is true and therefore the consequent is true. This chimes with what we tend to mean by 'if' in natural language. In the second case (TF) it also makes sense: the complex sentence is false because it rained and the pavement wasn't wet: this negates the truth of the expression. The final case (FF) is also straight forward. It didn't rain therefore the pavement wasn't wet, thus the overall assertion that rain implies wet pavements is retained. +The material conditional is perhaps the least intuitive of the logical connectives. The first case (TT) closely matches what we expect the connective to mean: it has rained so the pavement is wet. The antecedent is true and therefore the consequent is true. This chimes with what we tend to mean by 'if' in natural language. In the second case (TF) it also makes sense: the complex proposition is false because it rained and the pavement wasn't wet: this negates the truth of the expression. The final case (FF) is also straight forward. It didn't rain therefore the pavement wasn't wet, thus the overall assertion that rain implies wet pavements is retained. FT is less intuitive: @@ -84,7 +84,7 @@ It did not rain today. The pavement was wet. To some degree one just has to take these statements as axioms, whether or not they have intuitive sense is a secondary, more philosophical question. The semantic issues arise because we tacitly assume the material conditional to be a causal connective: there is something about the nature of **P** that _engenders_ or _brings about_ **Q** but causality is not a logical concern. -If we instead just focus on the simple sentences that comprise the truth value it is more plausible. In the case of FT we can say it didn't rain yet the pavement was wet does not stop the pavement being wet when it rains. The fact that I can pour a beer on the pavement thereby making it wet doesn't stop or render false the idea that the rain can also make the pavement wet. The same explanation covers the FF case: it hasn't rained and so the pavement is not wet does not contradict the assertion that when it rains the pavement will be wet. +If we instead just focus on the simple propositions that comprise the truth value it is more plausible. In the case of FT we can say it didn't rain yet the pavement was wet does not stop the pavement being wet when it rains. The fact that I can pour a beer on the pavement thereby making it wet doesn't stop or render false the idea that the rain can also make the pavement wet. The same explanation covers the FF case: it hasn't rained and so the pavement is not wet does not contradict the assertion that when it rains the pavement will be wet. Things are elucidated when we look at an equivalent expression of P ⊃ Q, ~P v Q: @@ -100,7 +100,7 @@ A disjunction is true whenever either disjunct is true so when both are false th ### Material biconditional (a.k.a equivalence) -The material biconditional equates to the English expression 'if and only if', as a conditional connective it therefore avoids some of the perplexity aroused by its material cousin. In this scenario both antecedent and consequent have to be true for the overall expression to be true. If either is false the complex sentence is false. Other ways of expressing the semantics of this connective is to say that one sentence implies the other or that **P** and **Q** are equivalent. +The material biconditional equates to the English expression 'if and only if', as a conditional connective it therefore avoids some of the perplexity aroused by its material cousin. In this scenario both antecedent and consequent have to be true for the overall expression to be true. If either is false the complex proposition is false. Other ways of expressing the semantics of this connective is to say that one proposition implies the other or that **P** and **Q** are equivalent. ``` If and only if James studies every day he will pass the exam. @@ -122,9 +122,9 @@ The last condition (FF) maybe requires some explanation: if he has not studied e --- -So far we have applied connectives to simple sentences. In so doing we generate complex sentences. However sentences and connectives are inherently generative: we can build more complex expressions from less complex parts, using more than one type of connective or several different connectives to make larger complex sentences and express more detailed logical conditions ans statements about the world. +So far we have applied connectives to simple propositions. In so doing we generate complex propositions. However propositions and connectives are inherently generative: we can build more complex expressions from less complex parts, using more than one type of connective or several different connectives to make larger complex propositions and express more detailed logical conditions ans statements about the world. -For example the sentence: +For example the proposition: ``` Socrates was either a philosopher or a drinker but he wasn't a politician. @@ -156,7 +156,7 @@ F F T F F F F F ``` -Let's walk through each case where S stands for the overall sentence. +Let's walk through each case where S stands for the overall proposition. 1. S is false if Socrates was a philosopher, a drinker and a politician. 1. **S is true if Socrates was a philosopher, a drinker but not a politician.** @@ -169,13 +169,13 @@ Let's walk through each case where S stands for the overall sentence. If we look just at the true cases for simplicity, it becomes obvious that the truth value of the whole is a function of the truth-values of the parts. -At the highest level of generality the sentence is a conjunction with two disjuncts: `P v Q` and `~R` . Therefore, for the sentence to be true both conjuncts must be true. The first conjunct is true just if one of the subordinate disjuncts is true (Socrates is either a philosopher, a drinker, or both). The second conjunct is true just if Socrates is not a politician. Thus there is only one variation for the second conjunct (not being a politician) and two variations for the first conjunct (being a drinker/being a philosopher) hence there are three cases where the overall sentence is true. +At the highest level of generality the proposition is a conjunction with two disjuncts: `P v Q` and `~R` . Therefore, for the proposition to be true both conjuncts must be true. The first conjunct is true just if one of the subordinate disjuncts is true (Socrates is either a philosopher, a drinker, or both). The second conjunct is true just if Socrates is not a politician. Thus there is only one variation for the second conjunct (not being a politician) and two variations for the first conjunct (being a drinker/being a philosopher) hence there are three cases where the overall proposition is true. ### Logical equivalence -Once we start working with complex sentences with more than one truth-functional connective it becomes clear that the same sentence expressed in natural language can be expressed formally more than one way and thus that in logical terms, both formal expressions are equivalent. We can prove this equivalence by comparing truth tables. +Once we start working with complex propositions with more than one truth-functional connective it becomes clear that the same proposition expressed in natural language can be expressed formally more than one way and thus that in logical terms, both formal expressions are equivalent. We can prove this equivalence by comparing truth tables. -For example the sentence: +For example the proposition: ``` I am going to the shops and the gym. @@ -263,7 +263,7 @@ The example above is a key equivalence that you will encounter a lot especially ## Enforcing binary connectives through bracketing -If we had a sentence of the form +If we had a proposition of the form ``` Socrates is man, is mortal and a philosopher. @@ -275,7 +275,7 @@ We could not write this as: P & Q & R ``` -This would not be a well-formed sentence because at most truth functional connectives can only connect two simple sentences. It would not be possible to generate truth conditions for this sentence in its current form. Instead we introduce brackets to enforce a binary grouping of simple sentences. In this instance, the placement of the brackets does not affect the accurate interpretation of the truth conditions of the compound, so the following two formalisations are equivalent: +This would not be a well-formed proposition because at most truth functional connectives can only connect two simple propositions. It would not be possible to generate truth conditions for this proposition in its current form. Instead we introduce brackets to enforce a binary grouping of simple propositions. In this instance, the placement of the brackets does not affect the accurate interpretation of the truth conditions of the compound, so the following two formalisations are equivalent: ``` (P & Q) & R diff --git a/Logic/Propositional_logic/Truth-trees.md b/Logic/Propositional_logic/Truth-trees.md index d71a40d..4a971d2 100644 --- a/Logic/Propositional_logic/Truth-trees.md +++ b/Logic/Propositional_logic/Truth-trees.md @@ -64,7 +64,7 @@ Using the definitions above, we can now define truth-functional consistency and The following is a truth tree for the set ${P \lor Q, \sim P }$: -![basic-open-tree 1.svg](../img/basic-open-tree%201.svg) +![basic-open-tree 1.svg](../_img/basic-open-tree%201.svg) ### Interpretation @@ -90,7 +90,7 @@ Invoking the truth-table highlights the differences between the two techniques. The following is a truth tree for the set ${A & \sim B, C, \sim A \lor \sim B }$. -![basic-closed-tree 1.svg](../img/basic-closed-tree%201.svg) +![basic-closed-tree 1.svg](../_img/basic-closed-tree%201.svg) ### Interpretation @@ -119,37 +119,37 @@ So far we have encountered the decomposition rules for conjunction (`&D`) and di ### Negated negation decomposition: `~~D` -![negated-negation-decomposition-rule 2.svg](../img/negated-negation-decomposition-rule%202.svg) +![negated-negation-decomposition-rule 2.svg](../_img/negated-negation-decomposition-rule%202.svg) Truth passes only if $P$ is true ### Conjunction decomposition: `&D` -![conjunction-decomposition-rule.svg](../img/conjunction-decomposition-rule.svg) +![conjunction-decomposition-rule.svg](../_img/conjunction-decomposition-rule.svg) Truth passes only $P$ and $Q$ are both true. ### Negated Conjunction decomposition: `~&D` -![negated-conjunction-decomposition-rule.svg](../img/negated-conjunction-decomposition-rule.svg) +![negated-conjunction-decomposition-rule.svg](../_img/negated-conjunction-decomposition-rule.svg) Truth passes if either $\sim P$ or $\sim Q$ is true. This rule is a consequence of the equivalence between $\sim (P & Q)$ and $\sim P \lor \sim Q$ , the first of DeMorgan’s Laws. ### Disjunction decomposition: `vD` -![disjunction-decomposition-rule.svg](../img/disjunction-decomposition-rule.svg) +![disjunction-decomposition-rule.svg](../_img/disjunction-decomposition-rule.svg) Truth passes if either $P$or $Q$ are true. ### Negated Disjunction decomposition: `~vD` -![negated-disjunction-decomposition-rule.svg](../img/negated-disjunction-decomposition-rule.svg) +![negated-disjunction-decomposition-rule.svg](../_img/negated-disjunction-decomposition-rule.svg) Truth passes if both $P$ and $Q$ are false. This rule is a consequence of the equivalence between $\sim (P \lor Q)$ and $\sim P & \sim Q$, the second of DeMorgan’s Laws. ### Conditional decomposition: `⊃D` -![conditional-decomposition-rule.svg](../img/conditional-decomposition-rule.svg) +![conditional-decomposition-rule.svg](../_img/conditional-decomposition-rule.svg) Truth passes if either $\sim P$ or $Q$ are true. This rule is a consequence of the equivalence between $P \supset Q$ and $\sim P \lor Q$ therefore this branch has the shape of a disjunction with $\sim P$ , $Q$ as its disjuncts. @@ -157,17 +157,17 @@ Truth passes if either $\sim P$ or $Q$ are true. This rule is a consequence of t Truth passes if both $P$ and $\sim Q$ are true. This is a consequence of the equivalence between $\sim (P \supset Q)$ and $P & \sim Q$. -![negated-conditional-decomposition-rule.svg](../img/negated-conditional-decomposition-rule.svg) +![negated-conditional-decomposition-rule.svg](../_img/negated-conditional-decomposition-rule.svg) ### Biconditional decomposition: `≡D` -![biconditional-decomposition-rule.drawio(1).svg](../img/biconditional-decomposition-rule.drawio%281%29.svg) +![biconditional-decomposition-rule.drawio(1).svg](../_img/biconditional-decomposition-rule.drawio%281%29.svg) Truth passes if either $P$ and $Q$ are true or $\sim P & \sim Q$ are true. This is an interesting rule because it combines the disjunction and conjunction tree shapes. ### Negated biconditional decomposition: `~≡D` -![negated-biconditional-decomposition-rule.drawio.svg](../img/negated-biconditional-decomposition-rule.drawio.svg) +![negated-biconditional-decomposition-rule.drawio.svg](../_img/negated-biconditional-decomposition-rule.drawio.svg) Truth passes if either $P$ and $\sim Q$ is true or if $\sim P$ and $Q$ is true. @@ -181,7 +181,7 @@ With truth-trees regardless of which order you decompose the set members, the co Here are some examples of these rules applied: -![complex-tree.svg](../img/complex-tree.svg) +![complex-tree.svg](../_img/complex-tree.svg) Observe that here we don’t bother to decompose the sentence on line 1. This is because, having decomposed the sentences on lines 2 and 3 we have arrived at a closed tree. It is therefore unnecessary to go any further for if two sentences in the set are inconsistent with each other, adding another sentence is not going to change the overall assignment of inconsistency. @@ -199,7 +199,7 @@ When we wish to assess [logical falsity](Logical%20truth%20and%20falsity.md#logi A logically false sentence cannot be true on any assignment. This is the same thing as an inconsistent set. Thus it will be represented in a truth tree as inconsistency which is disclosed via a closed tree. -![logical-falsity-tree.svg](../img/logical-falsity-tree.svg) +![logical-falsity-tree.svg](../_img/logical-falsity-tree.svg) ### Logical truth @@ -221,7 +221,7 @@ Recall that $P$ and $Q$ are [logically equivalent](Logical%20equivalence.md) jus > Sentences $P$ and $Q$ are truth-functionally equivalent if and only if the set $\sim (P \equiv Q)$ has a closed tree -![logical-equivalence-tree.svg](../img/logical-equivalence-tree.svg) +![logical-equivalence-tree.svg](../_img/logical-equivalence-tree.svg) ### Logical entailment and validity diff --git a/Mathematics/Prealgebra/Dividing_fractions.md b/Mathematics/Prealgebra/Dividing_fractions.md index aee7c3f..54d4e64 100644 --- a/Mathematics/Prealgebra/Dividing_fractions.md +++ b/Mathematics/Prealgebra/Dividing_fractions.md @@ -11,15 +11,15 @@ tags: Suppose you have the following shape: -![draw.io-Page-9.drawio 1.png](../../img/draw.io-Page-9.drawio.png) +![draw.io-Page-9.drawio 1.png](../../_img/draw.io-Page-9.drawio.png) One part is shaded. This represents one-eighth of the original shape. -![one-eighth-a.png](../../img/one-eighth-a.png) +![one-eighth-a.png](../../_img/one-eighth-a.png) Now imagine there are four instances of the shape and one-eighth remains shaded. How man one-eighths are there in four? -![draw.io-Page-9.drawio 2.png](../../img/draw.io-Page-9.drawio.png) +![draw.io-Page-9.drawio 2.png](../../_img/draw.io-Page-9.drawio.png) The shaded proportion represents $\frac{1}{8}$ of the shape. Imagine four of these shapes, how many eighths are there? diff --git a/Mathematics/Prealgebra/Equivalent_fractions.md b/Mathematics/Prealgebra/Equivalent_fractions.md index 88be83a..9d60978 100644 --- a/Mathematics/Prealgebra/Equivalent_fractions.md +++ b/Mathematics/Prealgebra/Equivalent_fractions.md @@ -9,7 +9,7 @@ tags: Two fractions are equivalent if they represent the same value. To begin with we can represent this visually: -![equiv-fractions.png](../../img/equiv-fractions.png) +![equiv-fractions.png](../../_img/equiv-fractions.png) _Each shaded area is taking up the same proportion of the whole._ diff --git a/Mathematics/Prealgebra/Prime_factorization.md b/Mathematics/Prealgebra/Prime_factorization.md index f141adb..8b9c076 100644 --- a/Mathematics/Prealgebra/Prime_factorization.md +++ b/Mathematics/Prealgebra/Prime_factorization.md @@ -16,10 +16,10 @@ Prime factorisation is the activity of expressing a composite number as the uniq > **Factor trees:** we take a number $n$ and break it down into two factors of $n$. We then repeat this process with the resulting factors working recursively until the numbers we are left with are primes. -![Untitled Diagram-Page-1.drawio.png](../../img/Untitled%20Diagram-Page-1.drawio.png) +![Untitled Diagram-Page-1.drawio.png](../../_img/Untitled%20Diagram-Page-1.drawio.png) _The prime factors of 27 are 2, 3, 3_ it doesn't matter which products we choose as the interim factors, we should always reach the same outcome: -![Untitled Diagram-Page-3.drawio 1.png](../../img/Untitled%20Diagram-Page-3.drawio%201.png) +![Untitled Diagram-Page-3.drawio 1.png](../../_img/Untitled%20Diagram-Page-3.drawio%201.png) -![Untitled Diagram-Page-2.drawio.png](../../img/Untitled%20Diagram-Page-2.drawio.png) +![Untitled Diagram-Page-2.drawio.png](../../_img/Untitled%20Diagram-Page-2.drawio.png) diff --git a/Mathematics/Prealgebra/Reducing_fractions.md b/Mathematics/Prealgebra/Reducing_fractions.md index 59aa053..376bfa5 100644 --- a/Mathematics/Prealgebra/Reducing_fractions.md +++ b/Mathematics/Prealgebra/Reducing_fractions.md @@ -68,7 +68,7 @@ This is still a bit long-winded however particularly when finding the factors of A better method is to utilise [prime factorization](Prime%20factorization.md) combined with the canceling technique. First we find the prime factors of both the numerator and denominator: -![drawio-Page-7.drawio.png](../../img/drawio-Page-7.drawio.png) +![drawio-Page-7.drawio.png](../../_img/drawio-Page-7.drawio.png) This gives us: @@ -133,7 +133,7 @@ _Reduce the following fraction to its lowest terms: $$\frac{14y^5}{-35y^3}$$_ - Apply [Prime factorization](Prime%20factorization.md): - ![draw.io-Page-8.drawio.png](../../img/draw.io-Page-8.drawio.png) + ![draw.io-Page-8.drawio.png](../../_img/draw.io-Page-8.drawio.png) - Cancel the coefficients and variable parts @@ -148,7 +148,7 @@ $$\frac{- 12xy^2}{ - 18xy^2}$$_ - Apply [Prime factorization](Prime%20factorization.md): -![draw.io-Page-8.drawio 1.png](../../img/draw.io-Page-8.drawio%201.png) +![draw.io-Page-8.drawio 1.png](../../_img/draw.io-Page-8.drawio%201.png) - Cancel the coefficients and variable parts diff --git a/Operating_Systems/Boot_process.md b/Operating_Systems/Boot_process.md index f6782c9..af729c6 100644 --- a/Operating_Systems/Boot_process.md +++ b/Operating_Systems/Boot_process.md @@ -46,7 +46,7 @@ Even though most modern computers use UEFI, it may still be referred to as BIOS The de facto standard boot loader for Linux is GRUB: Grand Unified Boot Loader. -![](/img/grub.jpg) +![](/_img/grub.jpg) You see the GRUB default menu when you first start a Linux machine. It will offer you various options for loading your installed OS or other OSs. GRUB is a filesystem like the main disk. If you press `e` in this screen you can view and edit specific boot parameters. Pressing `c` gives you access to the GRUB command line interface. This allows you to interact with GRUB in the same way as you would with any other filesystem, allowing for advanced configuration. diff --git a/Operating_Systems/Disks/Filesystems.md b/Operating_Systems/Disks/Filesystems.md index fcda7e9..d62ce75 100644 --- a/Operating_Systems/Disks/Filesystems.md +++ b/Operating_Systems/Disks/Filesystems.md @@ -51,7 +51,7 @@ touch test.txt Our `sda1` partition is now mounted at `mountpoint`. We can go ahead and create files. If we now look within the graphical file manager when we click on the `sda1` volume, we will see the new file we have created in `mountpoint`. -![](/img/mount-directory.png) +![](/_img/mount-directory.png) ## fstab diff --git a/Operating_Systems/Disks/What_are_disks.md b/Operating_Systems/Disks/What_are_disks.md index ac00f73..a4d9f76 100644 --- a/Operating_Systems/Disks/What_are_disks.md +++ b/Operating_Systems/Disks/What_are_disks.md @@ -20,7 +20,7 @@ A disk is a mass storage [block_device](/Operating_Systems/Devices.md) which we The following diagram represents the basic anatomy of a disk device. -![](/img/harddisk.png) +![](/_img/harddisk.png) - A disk is divided up into [partitions](/Operating_Systems/Disks/Partitions.md) which are subsections of the overall disk. The kernel presents each partition as a [block device](/Operating_Systems/Devices.md) as it would with an entire disk. - The disk dedicates a small part of its contents to a **partition table**: this defines the different partitions that comprise the total disk space. diff --git a/Operating_Systems/Relation_between_kernel_and_CPU.md b/Operating_Systems/Relation_between_kernel_and_CPU.md index d6a6653..9a35d24 100644 --- a/Operating_Systems/Relation_between_kernel_and_CPU.md +++ b/Operating_Systems/Relation_between_kernel_and_CPU.md @@ -14,7 +14,7 @@ It can be confusing to understand how the kernel and CPU interact with one anoth However as a process, the kernel is the 'first amongst equals' given that it is the core embodiment of the operating system. At boot time, the kernel is injected into memory and at this point the CPU _looks to this address_ in memory in order to source its first instruction. That's how the kernel gets going. It is the first instruction that the CPU fetches and this is what allows the kernel to play its mediatory role. However most of the fetch, decode, execute cycles of the CPU take place independently of the kernel. -![](/img/kernel-cpu-interaction.svg) +![](/_img/kernel-cpu-interaction.svg) > Fetch decode and execute refer to processor pipeline stages. They occur automatically as part of normal processor operation, the kernel doesn’t generally have any direct control over how that happens...When the boot loader loads the kernel, it points the CPU’s program counter to an entry point in the kernel’s code. From there, the CPU will continue executing (fetching decoding and executing) kernel code until you point the program counter to a userspace program, where it will continue executing userspace code until an interrupt points the program counter back into kernel code. That’s basically what the CPU will be doing from boot up to shut down; switching between executing kernel code and executing userspace code ([Reddit](https://www.reddit.com/r/osdev/comments/wdskj5/how_does_kernel_decide_if_use_cpu_or_gpu_after/)) diff --git a/Operating_Systems/Virtual_memory_and_the_MMU.md b/Operating_Systems/Virtual_memory_and_the_MMU.md index 6b42a02..15f22e7 100644 --- a/Operating_Systems/Virtual_memory_and_the_MMU.md +++ b/Operating_Systems/Virtual_memory_and_the_MMU.md @@ -13,7 +13,7 @@ Virtual memory is implemented at the level of the operating system and is an abs When virtual memory is used, the CPU handles physical memory allocation and presents this to the kernel as an idealised representation. This means that the kernel and, by extension, programs and processes do not need to think about accessing the real memory blocks. This reduces complexity because often memory will be allocated in places that are non-contiguous with similar running processes or be located in the cache or swap memory on the disk. -![](/img/virtual-memory-diagram.jpg) +![](/_img/virtual-memory-diagram.jpg) It would require considerable processing work for the kernel to be tracing these disparate memory sources at every instance. By working on an idealised (contiguous, unlimited) memory set the kernel can focus on task management and CPU sequencing as its primary task. diff --git a/Programming_Languages/Frameworks/React/Classes/Lifecycle_methods.md b/Programming_Languages/Frameworks/React/Classes/Lifecycle_methods.md index 4df47b5..6d9b020 100644 --- a/Programming_Languages/Frameworks/React/Classes/Lifecycle_methods.md +++ b/Programming_Languages/Frameworks/React/Classes/Lifecycle_methods.md @@ -37,7 +37,7 @@ The final phase is unmounting: when the component is removed from the DOM: 6. `componentWillUnmount()` -![React component lifecycle](../../../img/react-lifecycle.png) +![React component lifecycle](../../../_img/react-lifecycle.png) ## Side-effects: why lifecycle phases matter diff --git a/Programming_Languages/Node/Architecture/Event_loop.md b/Programming_Languages/Node/Architecture/Event_loop.md index 89d3466..1a1b1bc 100644 --- a/Programming_Languages/Node/Architecture/Event_loop.md +++ b/Programming_Languages/Node/Architecture/Event_loop.md @@ -21,7 +21,7 @@ Many backend frameworks are synchronous but multithreaded. This means that a thr If there was only one thread, this would be inefficient and unworkable. Therefore the framework will be multi-threaded: multiple request-response cycles can be executed at once by different threads. -![sync-thread.svg](/img/sync-thread.svg) +![sync-thread.svg](/_img/sync-thread.svg) To accomodate the ability to increase the scale of synchronous applications you need to be able to spawn more threads commensurate to increased demand. This increases the resource consumption of the framework (more cores, more memory etc). Moreover it is possible to reach a point where all threads are active and no more can be spawned. In this case there will simply be delays in the return of data. @@ -29,7 +29,7 @@ To accomodate the ability to increase the scale of synchronous applications you In contrast, Node only has a single thread but it works asynchronously, not synchronously. Thus it has a **single-threaded asynchronous architecture**. This means whilst there is only a single thread it can juggle responses by dispatching them asynchronously. When a request is made it sends it off and continues with its execution and handling new requests. Once these resolve, the data is returned to the main thread. -![async.svg](/img/async.svg) +![async.svg](/_img/async.svg) ## The Event Loop @@ -45,7 +45,7 @@ A running Node application is a single running process. Like everything that hap The Event Loop comprises six phases. The Event Loop starts at the moment Node begins to execute your `index.js` file or any other application entry point. These six phases create one cycle, or loop, equal to one **tick**. A Node.js process exits when there is no more pending work in the Event Loop, or when `process.exit()` is called manually. A program only runs for as long as there are tasks queued in the Event Loop, or present on the [call stack](/Software_Engineering/Call_stack.md). -![](/img/node-event-loop.svg) +![](/_img/node-event-loop.svg) The phases are as follows: diff --git a/Programming_Languages/Node/Modules/Package_management.md b/Programming_Languages/Node/Modules/Package_management.md index 26c147f..06bac45 100644 --- a/Programming_Languages/Node/Modules/Package_management.md +++ b/Programming_Languages/Node/Modules/Package_management.md @@ -28,7 +28,7 @@ We can pinpoint specific dependencies in the `package.json`, e.g. `npm view [pac See whether your dependency version is out of date use `npm outdated`. This gives us a table, for example: -![Pasted image 20220411082627.png](/img/Pasted_image_20220411082627.png) +![Pasted image 20220411082627.png](/_img/Pasted_image_20220411082627.png) - _Latest_ tells us the latest release available from the developers - _Wanted_ tells us the version that our `package.json` rules target. To take the first dependency as an example. We must have set our SemVer syntax to `^0.4.x` since it is telling us that there is a minor release that is more recent than the one we have installed but is not advising that we update to the latest major release. diff --git a/Programming_Languages/Node/REST_APIs/1_GET.md b/Programming_Languages/Node/REST_APIs/1_GET.md index fc8a827..a077811 100644 --- a/Programming_Languages/Node/REST_APIs/1_GET.md +++ b/Programming_Languages/Node/REST_APIs/1_GET.md @@ -19,7 +19,7 @@ router.get("/", (req, res) => { Our server is now set up: -![](/img/server-listening.png) +![](/_img/server-listening.png) > When creating our API this structure of creating handlers for specific routes will be iterated. Every endpoint will be specified with `[app].[http_request_type]` and followed by a callback. diff --git a/README.md b/README.md new file mode 100644 index 0000000..8490919 --- /dev/null +++ b/README.md @@ -0,0 +1,3 @@ +# computer-science + +This repository contains notes from my autodidactic study of Computer Science. As well as standard CS curricula it also houses notes related to my professional development as a software engineer. So there is a lot of practical content mixed in, such as topics in DevOps, Git, shell scripting etc. I find it easier to have everything in one place and cross-referenced through YAML. diff --git a/Theory_of_Computation/Defining_a_computer.md b/Theory_of_Computation/Defining_a_computer.md index 19798da..ab60e65 100644 --- a/Theory_of_Computation/Defining_a_computer.md +++ b/Theory_of_Computation/Defining_a_computer.md @@ -11,7 +11,7 @@ tags: This sets a general purpose computer aside from a special-purpose computer, like the one you might find in your dishwasher which may have its instructions hardwired or coded into the machine. Special purpose computers only perform a single set of tasks according to prewritten instructions. We’ll take the term _computer_ to mean general purpose computer. Simplified model of what a computer is: -![1.4-Input-Process-Output.png](../img/1.4-Input-Process-Output.png) +![1.4-Input-Process-Output.png](../_img/1.4-Input-Process-Output.png) Although the input, output and storage parts of a computer are very important, they will not be the focus of this course. Instead we are going to learn all about the process part, which will focus on how the computer is able to follow instructions to make calculations. @@ -35,9 +35,9 @@ Although the input, output and storage parts of a computer are very important, t - But as these machines were expensive and slow, people used pre-computed tables in book form generated by human computers. Useful particularly for things like square roots. - Similarly range tables were created that aided the military in calculating distances for gunboat artillery which factored in contextual factors like wind, drift, slope and elevation. These were used well into WW2 but they were limited to the particular type of cannon or shell -![Screenshot_2020-08-09_at_21.32.54 1.png](../img/Screenshot_2020-08-09_at_21.32.54%201.png) +![Screenshot_2020-08-09_at_21.32.54 1.png](../_img/Screenshot_2020-08-09_at_21.32.54%201.png) -![Screenshot_2020-08-09_at_21.34.48.png](../img/Screenshot_2020-08-09_at_21.34.48.png) +![Screenshot_2020-08-09_at_21.34.48.png](../_img/Screenshot_2020-08-09_at_21.34.48.png) > Before the invention of actual computers, 'computer' was a job-title denoting people who were employed to conduct complex calculations, sometimes with the aid of machinery, but most often not. This persisted until the late 18th century when the word changed to include devices like adding machines. diff --git a/Theory_of_Computation/Turing_machines.md b/Theory_of_Computation/Turing_machines.md index 4bfa99c..6573e36 100644 --- a/Theory_of_Computation/Turing_machines.md +++ b/Theory_of_Computation/Turing_machines.md @@ -10,7 +10,7 @@ tags: A Turing Machine consists of an infinitely long tape, that has been divided up into cells. Each cell can contain either a 1, a 0 or an empty space. Above one cell of the tape is a head, which can either move left or right, and can read the symbols written in the cells. The head is also capable of erasing symbols and writing new symbols into the cells. -![Turing_machines_01.gif](../img/Turing_machines_01.gif) +![Turing_machines_01.gif](../_img/Turing_machines_01.gif) The direction that the head moves, which values it erases, and which values it writes in, are dependent on a set of instructions provided to the machine.0 Different sets of instructions can be divided into **states.** States are like sub-routines and can themselves feature as part of instructions. diff --git a/_img/1.4-Input-Process-Output.png b/_img/1.4-Input-Process-Output.png new file mode 100644 index 0000000..9f804e1 Binary files /dev/null and b/_img/1.4-Input-Process-Output.png differ diff --git a/_img/3-bit-adder-diagram.png b/_img/3-bit-adder-diagram.png new file mode 100644 index 0000000..7d993e7 Binary files /dev/null and b/_img/3-bit-adder-diagram.png differ diff --git a/_img/74181aluschematic.png b/_img/74181aluschematic.png new file mode 100644 index 0000000..161699e Binary files /dev/null and b/_img/74181aluschematic.png differ diff --git a/_img/FL-Databases-1.5_terminology.gif b/_img/FL-Databases-1.5_terminology.gif new file mode 100644 index 0000000..1040c3d Binary files /dev/null and b/_img/FL-Databases-1.5_terminology.gif differ diff --git a/_img/LMC_5.gif b/_img/LMC_5.gif new file mode 100644 index 0000000..3399182 Binary files /dev/null and b/_img/LMC_5.gif differ diff --git a/_img/Memory-Hierarchy.jpg b/_img/Memory-Hierarchy.jpg new file mode 100644 index 0000000..4c9bba8 Binary files /dev/null and b/_img/Memory-Hierarchy.jpg differ diff --git a/_img/ORelim1.png b/_img/ORelim1.png new file mode 100644 index 0000000..75731b0 Binary files /dev/null and b/_img/ORelim1.png differ diff --git a/_img/ORelim2.png b/_img/ORelim2.png new file mode 100644 index 0000000..3bb7113 Binary files /dev/null and b/_img/ORelim2.png differ diff --git a/_img/Pasted_image_20220319135558.png b/_img/Pasted_image_20220319135558.png new file mode 100644 index 0000000..6298a65 Binary files /dev/null and b/_img/Pasted_image_20220319135558.png differ diff --git a/_img/Pasted_image_20220319135805.png b/_img/Pasted_image_20220319135805.png new file mode 100644 index 0000000..37109dd Binary files /dev/null and b/_img/Pasted_image_20220319135805.png differ diff --git a/_img/Pasted_image_20220319135823.png b/_img/Pasted_image_20220319135823.png new file mode 100644 index 0000000..2b5fd00 Binary files /dev/null and b/_img/Pasted_image_20220319135823.png differ diff --git a/_img/Pasted_image_20220319174839.png b/_img/Pasted_image_20220319174839.png new file mode 100644 index 0000000..1c00b90 Binary files /dev/null and b/_img/Pasted_image_20220319174839.png differ diff --git a/_img/Pasted_image_20220411082627.png b/_img/Pasted_image_20220411082627.png new file mode 100644 index 0000000..82fd434 Binary files /dev/null and b/_img/Pasted_image_20220411082627.png differ diff --git a/_img/REST_request-load.png b/_img/REST_request-load.png new file mode 100644 index 0000000..74792c2 Binary files /dev/null and b/_img/REST_request-load.png differ diff --git a/_img/Screenshot_2020-08-09_at_21.34.48.png b/_img/Screenshot_2020-08-09_at_21.34.48.png new file mode 100644 index 0000000..bbbb066 Binary files /dev/null and b/_img/Screenshot_2020-08-09_at_21.34.48.png differ diff --git a/_img/Screenshot_2021-05-11_at_18.51.02.png b/_img/Screenshot_2021-05-11_at_18.51.02.png new file mode 100644 index 0000000..15ee66a Binary files /dev/null and b/_img/Screenshot_2021-05-11_at_18.51.02.png differ diff --git a/_img/Screenshot_2021-05-11_at_18.55.23.png b/_img/Screenshot_2021-05-11_at_18.55.23.png new file mode 100644 index 0000000..1da93a9 Binary files /dev/null and b/_img/Screenshot_2021-05-11_at_18.55.23.png differ diff --git a/_img/Turing_machines_01.gif b/_img/Turing_machines_01.gif new file mode 100644 index 0000000..974e3b3 Binary files /dev/null and b/_img/Turing_machines_01.gif differ diff --git a/_img/analog-digital.svg b/_img/analog-digital.svg new file mode 100644 index 0000000..35f441a --- /dev/null +++ b/_img/analog-digital.svg @@ -0,0 +1,38 @@ + + + + + + + + + + + + + + + + + + + + + 12 + 82 + 78 + 63 + 39 + 70 + 44 + 9 + -36 + -69 + -80 + -59 + -14 + 42 + Analog + Digital + + \ No newline at end of file diff --git a/_img/and-gate-new-2.png b/_img/and-gate-new-2.png new file mode 100644 index 0000000..58eab1d Binary files /dev/null and b/_img/and-gate-new-2.png differ diff --git a/_img/and-transistor.png b/_img/and-transistor.png new file mode 100644 index 0000000..a18d128 Binary files /dev/null and b/_img/and-transistor.png differ diff --git a/_img/apollo-explorer.png b/_img/apollo-explorer.png new file mode 100644 index 0000000..4725eeb Binary files /dev/null and b/_img/apollo-explorer.png differ diff --git a/_img/async.svg b/_img/async.svg new file mode 100644 index 0000000..fd85032 --- /dev/null +++ b/_img/async.svg @@ -0,0 +1,4 @@ + + + +
asynchronous
asynchronousText is not SVG - cannot display \ No newline at end of file diff --git a/_img/atom-diagram.svg b/_img/atom-diagram.svg new file mode 100644 index 0000000..bde130b --- /dev/null +++ b/_img/atom-diagram.svg @@ -0,0 +1 @@ +Zeichenfläche 1 \ No newline at end of file diff --git a/_img/basic-circuit.png b/_img/basic-circuit.png new file mode 100644 index 0000000..f72f364 Binary files /dev/null and b/_img/basic-circuit.png differ diff --git a/_img/bi-intro.png b/_img/bi-intro.png new file mode 100644 index 0000000..23a0572 Binary files /dev/null and b/_img/bi-intro.png differ diff --git a/_img/biconditional-elim.png b/_img/biconditional-elim.png new file mode 100644 index 0000000..c34918b Binary files /dev/null and b/_img/biconditional-elim.png differ diff --git a/_img/breadboard-DIP.jpg b/_img/breadboard-DIP.jpg new file mode 100644 index 0000000..4e54dec Binary files /dev/null and b/_img/breadboard-DIP.jpg differ diff --git a/_img/breakdown.svg b/_img/breakdown.svg new file mode 100644 index 0000000..3258648 --- /dev/null +++ b/_img/breakdown.svg @@ -0,0 +1,39 @@ + + + Artboard + + + + + + + + + + + + + + O(1) + + + + + + O(n) + + + + + + O(1) + + + + + + O(1) + + + + \ No newline at end of file diff --git a/_img/cell-comparison.svg b/_img/cell-comparison.svg new file mode 100644 index 0000000..65a4a4f --- /dev/null +++ b/_img/cell-comparison.svg @@ -0,0 +1,4 @@ + + + +
Current
Current
Sum of all cells
Sum of all cells
Series-Parallel
Series-Parallel
Series
Series
Parallel
Parallel
Same for all cells
Same for all cells
Sum of all cells
Sum of all cells
Voltage
Voltage
Sum of all cells
Sum of all cells
Same for all cells
Same for all cells
Sum of all cells
Sum of all cellsText is not SVG - cannot display \ No newline at end of file diff --git a/_img/charge-cylinder.svg b/_img/charge-cylinder.svg new file mode 100644 index 0000000..6325077 --- /dev/null +++ b/_img/charge-cylinder.svg @@ -0,0 +1,4 @@ + + + + \ No newline at end of file diff --git a/_img/circ-batt-final.svg b/_img/circ-batt-final.svg new file mode 100644 index 0000000..1d2a2ae --- /dev/null +++ b/_img/circ-batt-final.svg @@ -0,0 +1,4 @@ + + + +
1.5 V
1.5 VText is not SVG - cannot display \ No newline at end of file diff --git a/_img/clock_pulses.png b/_img/clock_pulses.png new file mode 100644 index 0000000..7e69aaa Binary files /dev/null and b/_img/clock_pulses.png differ diff --git a/_img/complex-tree.svg b/_img/complex-tree.svg new file mode 100644 index 0000000..9cbba30 --- /dev/null +++ b/_img/complex-tree.svg @@ -0,0 +1,4 @@ + + + +
C
C
7~~D
7~~D
5
5
~C
~C
SM
SM
1
1
2 ~vD
2 ~vD
4
4
~(C v A)
~(C v A)
SM
SM
2
2
A ⊃ (B & ~C)
A ⊃ (B & ~C)
C ≡ ~A
C ≡ ~A
SM
SM
3
3
~C
~C
~A
~A
~~A
~~A
~A
~A
4
4
6
6
7
7
A
A
5
5
2 ~vD
2 ~vD
3≡D
3≡D
3≡D
3≡DViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/cond-elim.png b/_img/cond-elim.png new file mode 100644 index 0000000..993a336 Binary files /dev/null and b/_img/cond-elim.png differ diff --git a/_img/cond-intro.png b/_img/cond-intro.png new file mode 100644 index 0000000..5287392 Binary files /dev/null and b/_img/cond-intro.png differ diff --git a/_img/conditional-decomposition-rule.svg b/_img/conditional-decomposition-rule.svg new file mode 100644 index 0000000..a400a50 --- /dev/null +++ b/_img/conditional-decomposition-rule.svg @@ -0,0 +1,4 @@ + + + +
~P
~P
Q
Q
P ⊃ Q
P ⊃ Q
1
1
2
2
SM
SM
1⊃D
1⊃DViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/conjunc-elim.png b/_img/conjunc-elim.png new file mode 100644 index 0000000..fd66290 Binary files /dev/null and b/_img/conjunc-elim.png differ diff --git a/_img/conjunc-intro.png b/_img/conjunc-intro.png new file mode 100644 index 0000000..3a8d642 Binary files /dev/null and b/_img/conjunc-intro.png differ diff --git a/_img/conjunction-decomposition-rule.svg b/_img/conjunction-decomposition-rule.svg new file mode 100644 index 0000000..5abcbd2 --- /dev/null +++ b/_img/conjunction-decomposition-rule.svg @@ -0,0 +1,4 @@ + + + +
P & Q
P & Q
1
1
2
2
3
3
P 
P 
Q
Q
SM
SM
1&D
1&D
1&D
1&DViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/derivation_from_contradiction.png b/_img/derivation_from_contradiction.png new file mode 100644 index 0000000..2c81072 Binary files /dev/null and b/_img/derivation_from_contradiction.png differ diff --git a/_img/diode-led.png b/_img/diode-led.png new file mode 100644 index 0000000..00c3334 Binary files /dev/null and b/_img/diode-led.png differ diff --git a/_img/diode.png b/_img/diode.png new file mode 100644 index 0000000..fddfca4 Binary files /dev/null and b/_img/diode.png differ diff --git a/_img/dipole-again.svg b/_img/dipole-again.svg new file mode 100644 index 0000000..13cac44 --- /dev/null +++ b/_img/dipole-again.svg @@ -0,0 +1,4 @@ + + + +
E
E
North
North
E
E
South
South
Spin
Spin
Spin
SpinText is not SVG - cannot display \ No newline at end of file diff --git a/_img/disjunc-elim.png b/_img/disjunc-elim.png new file mode 100644 index 0000000..0127c59 Binary files /dev/null and b/_img/disjunc-elim.png differ diff --git a/_img/disjunc-intro.png b/_img/disjunc-intro.png new file mode 100644 index 0000000..6047493 Binary files /dev/null and b/_img/disjunc-intro.png differ diff --git a/_img/disjunction-decomposition-rule.svg b/_img/disjunction-decomposition-rule.svg new file mode 100644 index 0000000..144b2e8 --- /dev/null +++ b/_img/disjunction-decomposition-rule.svg @@ -0,0 +1,4 @@ + + + +
P
P
Q
Q
P v Q
P v Q
1
1
2
2
SM
SM
1vD
1vDViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/draw.io-Page-8.drawio.png b/_img/draw.io-Page-8.drawio.png new file mode 100644 index 0000000..8c111e9 Binary files /dev/null and b/_img/draw.io-Page-8.drawio.png differ diff --git a/_img/draw.io-Page-9.drawio.png b/_img/draw.io-Page-9.drawio.png new file mode 100644 index 0000000..9614777 Binary files /dev/null and b/_img/draw.io-Page-9.drawio.png differ diff --git a/_img/drawio-Page-7.drawio.png b/_img/drawio-Page-7.drawio.png new file mode 100644 index 0000000..e86a851 Binary files /dev/null and b/_img/drawio-Page-7.drawio.png differ diff --git a/_img/dsfdsfsdfwe.png b/_img/dsfdsfsdfwe.png new file mode 100644 index 0000000..207ba84 Binary files /dev/null and b/_img/dsfdsfsdfwe.png differ diff --git a/_img/em-spectrum.jpg b/_img/em-spectrum.jpg new file mode 100644 index 0000000..46a2191 Binary files /dev/null and b/_img/em-spectrum.jpg differ diff --git a/_img/em-wave.gif b/_img/em-wave.gif new file mode 100644 index 0000000..8faba2c Binary files /dev/null and b/_img/em-wave.gif differ diff --git a/_img/equiv-fractions.png b/_img/equiv-fractions.png new file mode 100644 index 0000000..ddd0dbd Binary files /dev/null and b/_img/equiv-fractions.png differ diff --git a/_img/four-bit-adder.png b/_img/four-bit-adder.png new file mode 100644 index 0000000..649c9b3 Binary files /dev/null and b/_img/four-bit-adder.png differ diff --git a/_img/full-adder-new.png b/_img/full-adder-new.png new file mode 100644 index 0000000..8eb9df0 Binary files /dev/null and b/_img/full-adder-new.png differ diff --git a/_img/graphQL_request_load.png b/_img/graphQL_request_load.png new file mode 100644 index 0000000..df97e79 Binary files /dev/null and b/_img/graphQL_request_load.png differ diff --git a/_img/graphql-architecture.png b/_img/graphql-architecture.png new file mode 100644 index 0000000..b56b208 Binary files /dev/null and b/_img/graphql-architecture.png differ diff --git a/_img/graphql-journey-two.svg b/_img/graphql-journey-two.svg new file mode 100644 index 0000000..949cd30 --- /dev/null +++ b/_img/graphql-journey-two.svg @@ -0,0 +1,4 @@ + + + +
CLIENT
CLIENT
SERVER
SERVER
convert query to string 
and send to
server as POST or
GET request
convert query to string...
Parse string and 
convert to an Abstract Syntax Tree
Parse string and...
Using the AST, validate the query against the types and fields of the GraphQL schema
Using the AST, validate...
Yes
Yes
No
No
Error?
Error?
field
field
resolver
resolver
Convert to JSON object
matching shape of client query
Convert to JSON object...
Assign object to `data` key in HTTP response body
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Binary
Binary
Hex
Hex
Decimal
Decimal
0b00000000
0b00000000
0x00
0x00
0
0
0b01010101
0b01010101
0x55
0x55
85
85
0b10101010
0b10101010
0xAA
0xAA
170
170
0b11111111
0b11111111
0xFF
0xFF
255
255Text is not SVG - cannot display \ No newline at end of file diff --git a/_img/ground-symbol.png b/_img/ground-symbol.png new file mode 100644 index 0000000..7c7be5d Binary files /dev/null and b/_img/ground-symbol.png differ diff --git a/_img/grub.jpg b/_img/grub.jpg new file mode 100644 index 0000000..58cb270 Binary files /dev/null and b/_img/grub.jpg differ diff --git a/_img/half-adder-gates-three.png b/_img/half-adder-gates-three.png new file mode 100644 index 0000000..0469bc3 Binary files /dev/null and b/_img/half-adder-gates-three.png differ diff --git a/_img/half-adder-new.png b/_img/half-adder-new.png new file mode 100644 index 0000000..45dc092 Binary files /dev/null and b/_img/half-adder-new.png differ diff --git a/_img/harddisk.png b/_img/harddisk.png new file mode 100644 index 0000000..5f5ee0d Binary files /dev/null and b/_img/harddisk.png differ diff --git a/_img/hardware-abstraction-hierarchy.png b/_img/hardware-abstraction-hierarchy.png new file mode 100644 index 0000000..7251df8 Binary files /dev/null and b/_img/hardware-abstraction-hierarchy.png differ diff --git a/_img/hardware-sim-basic.png b/_img/hardware-sim-basic.png new file mode 100644 index 0000000..52a0049 Binary files /dev/null and b/_img/hardware-sim-basic.png differ diff --git a/_img/hd-sim-test.png b/_img/hd-sim-test.png new file mode 100644 index 0000000..f6775dd Binary files /dev/null and b/_img/hd-sim-test.png differ diff --git a/_img/hertz_wave_freq.gif b/_img/hertz_wave_freq.gif new file mode 100644 index 0000000..0fd7c0f Binary files /dev/null and b/_img/hertz_wave_freq.gif differ diff --git a/_img/hexadecimal-to-bytes.svg b/_img/hexadecimal-to-bytes.svg new file mode 100644 index 0000000..99cfb98 --- /dev/null +++ b/_img/hexadecimal-to-bytes.svg @@ -0,0 +1,4 @@ + + + +
8 A 5 2 F F 0 0
8 A 5 2 F F 0...
1000
1000
1010
1010
0101
0101
0010
0010
1111
1111
1111
1111
0000
0000
0000
0000
1 byte (8-bits)
1 byte (8-bits)
2 bytes (16-bits)
2 bytes (16-bits)
4 bytes (32-bits)
4 bytes (32-bits)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1Text is not SVG - cannot display \ No newline at end of file diff --git a/_img/htop.png b/_img/htop.png new file mode 100644 index 0000000..a97cd4b Binary files /dev/null and b/_img/htop.png differ diff --git a/_img/integrated-circuit.jpeg b/_img/integrated-circuit.jpeg new file mode 100644 index 0000000..71b6598 Binary files /dev/null and b/_img/integrated-circuit.jpeg differ diff --git a/_img/javascript-recursion.png b/_img/javascript-recursion.png new file mode 100644 index 0000000..b232421 Binary files /dev/null and b/_img/javascript-recursion.png differ diff --git a/_img/jk-flip-flops.png b/_img/jk-flip-flops.png new file mode 100644 index 0000000..f83dcdc Binary files /dev/null and b/_img/jk-flip-flops.png differ diff --git a/_img/journald.png b/_img/journald.png new file mode 100644 index 0000000..2781425 Binary files /dev/null and b/_img/journald.png differ diff --git a/_img/kernel-cpu-interaction.svg b/_img/kernel-cpu-interaction.svg new file mode 100644 index 0000000..0706e8c --- /dev/null +++ b/_img/kernel-cpu-interaction.svg @@ -0,0 +1,4 @@ + + + +
Locate kernel (OS)
Locate kernel (OS)

Disk
 Disk
Load kernel 
Load kernel 
Boot
Boot
Memory
Memory
Kernel
Kernel
Relay instructions
Relay instructions
CPU
CPU
USER SPACE
USER SPACE
Toggle
control
Toggle...
Fetch,
decode,
execute
Fetch,...
Shutdown
Shutdown
Shell
Shell
GUI
GUI
Schematic of role and lifecycle of the kernel
relative to the processor
and user space 
Schematic of role and lifecycle of the kernel...
 same entity/ location
same entity/ loc...
interaction between different entities
interaction between different enti...
CPU and kernel presented as logically distinct althought kernel is a running CPU process
CPU and kernel presente...Text is not SVG - cannot display \ No newline at end of file diff --git a/_img/lin.svg b/_img/lin.svg new file mode 100644 index 0000000..f207dd0 --- /dev/null +++ b/_img/lin.svg @@ -0,0 +1 @@ +01234567RUNTIMEn \ No newline at end of file diff --git a/_img/logical-equivalence-tree.svg b/_img/logical-equivalence-tree.svg new file mode 100644 index 0000000..bb78612 --- /dev/null +++ b/_img/logical-equivalence-tree.svg @@ -0,0 +1,4 @@ + + + +
P ⊃ Q
P ⊃ Q
5
5
~P v Q
~P v Q
SM
SM
1
1
1 ~≡D
1 ~≡D
4
4
2
2
(P ⊃ Q)  ≡ (~P v Q)
(P ⊃ Q)  ≡ (~P v Q)
3
3
P
P
4
4
7
7
3~⊃D
3~⊃D
~(P ⊃ Q)
~(P ⊃ Q)
~(~P v ~Q)
~(~P v ~Q)
6
6
1 ~≡D
1 ~≡D
~Q
~Q
3~⊃D
3~⊃D
P
P
~Q
~Q
5
5
~~P
~~P
~Q
~Q
P
P
~P
~P
Q
Q
9
9
8
8
8
8
9
9
10
10
2~⊃D
2~⊃D
3vD
3vD
2~vD
2~vD
2~vD
2~vD
7~~vD
7~~vDViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/logical-falsity-tree.svg b/_img/logical-falsity-tree.svg new file mode 100644 index 0000000..4e0c22c --- /dev/null +++ b/_img/logical-falsity-tree.svg @@ -0,0 +1,4 @@ + + + +
~P
~P
~Q
~Q
SM
SM
1
1
2&D
2&D
4
4
P & Q
P & Q
1&D
1&D
2
2
(P & Q) & ~(P & Q)
(P & Q) & ~(P & Q)
~(P & Q)
~(P & Q)
1&D
1&D
3
3
P
P
4
4
3&~D
3&~D
2&D
2&D
5
5
Q
Q
5
5Viewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/lsof.png b/_img/lsof.png new file mode 100644 index 0000000..8a8b5d5 Binary files /dev/null and b/_img/lsof.png differ diff --git a/_img/magnetic_field.png b/_img/magnetic_field.png new file mode 100644 index 0000000..e82e190 Binary files /dev/null and b/_img/magnetic_field.png differ diff --git a/_img/memory-flow.svg b/_img/memory-flow.svg new file mode 100644 index 0000000..ab78d87 --- /dev/null +++ b/_img/memory-flow.svg @@ -0,0 +1,4 @@ + + + +
CPU
CPU
L1 
CACHE
L1...
L2 CACHE
L2 CACHE
ADDRESS BUS
ADDRESS BUS
DATA BUS
DATA BUS
DRAM
DRAMText is not SVG - cannot display \ No newline at end of file diff --git a/_img/mongo-collection.png b/_img/mongo-collection.png new file mode 100644 index 0000000..227ae90 Binary files /dev/null and b/_img/mongo-collection.png differ diff --git a/_img/mongo-compass.png b/_img/mongo-compass.png new file mode 100644 index 0000000..8ecbab2 Binary files /dev/null and b/_img/mongo-compass.png differ diff --git a/_img/mongo-db-structure.svg b/_img/mongo-db-structure.svg new file mode 100644 index 0000000..6b1e2fb --- /dev/null +++ b/_img/mongo-db-structure.svg @@ -0,0 +1,4 @@ + + + +
Collection
Collection
Database
Database
Collection
Collection
Document
Document
Document
Document
Document
Document
Document
Document

Mongo database structure

Mongo database structureText is not SVG - cannot display \ No newline at end of file diff --git a/_img/mongo-doc-added.png b/_img/mongo-doc-added.png new file mode 100644 index 0000000..a45847f Binary files /dev/null and b/_img/mongo-doc-added.png differ diff --git a/_img/mongoose-hierarchy.svg b/_img/mongoose-hierarchy.svg new file mode 100644 index 0000000..15091f1 --- /dev/null +++ b/_img/mongoose-hierarchy.svg @@ -0,0 +1,4 @@ + + + +
Schema
Schema
Model 
Model 
Object instance
Object instanceSchema
const personSchema = new
   mongoose.Schema({
name: String,
age: Number
   })
const personSchema = new...Model
const Person = mongoose.model
("Person", personSchema)
const Person = mongoose.model...Object


const thomas = new Person({
   name: 'Thomas Bishop',
   age: 34
})
const thomas = new Person({...

Mongoose data hierarchy

Mongoose data hierarchyText is not SVG - cannot display \ No newline at end of file diff --git a/_img/motherboard-pi.jpg b/_img/motherboard-pi.jpg new file mode 100644 index 0000000..07c8c91 Binary files /dev/null and b/_img/motherboard-pi.jpg differ diff --git a/_img/mount-directory.png b/_img/mount-directory.png new file mode 100644 index 0000000..c522d2d Binary files /dev/null and b/_img/mount-directory.png differ diff --git a/_img/multi_on_off.gif b/_img/multi_on_off.gif new file mode 100644 index 0000000..f7c90ea Binary files /dev/null and b/_img/multi_on_off.gif differ diff --git a/_img/multiple_circuits.gif b/_img/multiple_circuits.gif new file mode 100644 index 0000000..c298651 Binary files /dev/null and b/_img/multiple_circuits.gif differ diff --git a/_img/multiplication_01.gif b/_img/multiplication_01.gif new file mode 100644 index 0000000..ee3839e Binary files /dev/null and b/_img/multiplication_01.gif differ diff --git a/_img/multiplication_02.gif b/_img/multiplication_02.gif new file mode 100644 index 0000000..26a7ef7 Binary files /dev/null and b/_img/multiplication_02.gif differ diff --git a/_img/multiplication_03.gif b/_img/multiplication_03.gif new file mode 100644 index 0000000..3dd5bb1 Binary files /dev/null and b/_img/multiplication_03.gif differ diff --git a/_img/multiplication_04.gif b/_img/multiplication_04.gif new file mode 100644 index 0000000..54f055e Binary files /dev/null and b/_img/multiplication_04.gif differ diff --git a/_img/nand-gate-new.png b/_img/nand-gate-new.png new file mode 100644 index 0000000..ca27c16 Binary files /dev/null and b/_img/nand-gate-new.png differ diff --git a/_img/nand-mem-demonstrated.gif b/_img/nand-mem-demonstrated.gif new file mode 100644 index 0000000..c8af9a7 Binary files /dev/null and b/_img/nand-mem-demonstrated.gif differ diff --git a/_img/nand-mem-first.gif b/_img/nand-mem-first.gif new file mode 100644 index 0000000..927aa81 Binary files /dev/null and b/_img/nand-mem-first.gif differ diff --git a/_img/nand-mem-second.gif b/_img/nand-mem-second.gif new file mode 100644 index 0000000..035f4e6 Binary files /dev/null and b/_img/nand-mem-second.gif differ diff --git a/_img/nand_latch_logic_circuit.png b/_img/nand_latch_logic_circuit.png new file mode 100644 index 0000000..631f722 Binary files /dev/null and b/_img/nand_latch_logic_circuit.png differ diff --git a/_img/negate-elim.png b/_img/negate-elim.png new file mode 100644 index 0000000..043992c Binary files /dev/null and b/_img/negate-elim.png differ diff --git a/_img/negate-intro.png b/_img/negate-intro.png new file mode 100644 index 0000000..0c2e920 Binary files /dev/null and b/_img/negate-intro.png differ diff --git a/_img/negated-biconditional-decomposition-rule.drawio.svg b/_img/negated-biconditional-decomposition-rule.drawio.svg new file mode 100644 index 0000000..38228e9 --- /dev/null +++ b/_img/negated-biconditional-decomposition-rule.drawio.svg @@ -0,0 +1,4 @@ + + + +
P
P
Q
Q
~(P ≡ Q)
~(P ≡ Q)
1
1
2
2
SM
SM
~1≡D
~1≡D
~P
~P
~Q
~Q
3
3
~1≡D
~1≡DViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/negated-conditional-decomposition-rule.svg b/_img/negated-conditional-decomposition-rule.svg new file mode 100644 index 0000000..bc8e052 --- /dev/null +++ b/_img/negated-conditional-decomposition-rule.svg @@ -0,0 +1,4 @@ + + + +
~(P ⊃ Q)
~(P ⊃ Q)
1
1
2
2
3
3
P 
P 
~Q
~Q
SM
SM
1~⊃D
1~⊃D
1~⊃D
1~⊃DViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/negated-conjunction-decomposition-rule.svg b/_img/negated-conjunction-decomposition-rule.svg new file mode 100644 index 0000000..0a7a24c --- /dev/null +++ b/_img/negated-conjunction-decomposition-rule.svg @@ -0,0 +1,4 @@ + + + +
~P
~P
~Q
~Q
~(P & Q)
~(P & Q)
1
1
2
2
SM
SM
~&D
~&DViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/negated-disjunction-decomposition-rule.svg b/_img/negated-disjunction-decomposition-rule.svg new file mode 100644 index 0000000..21b10e1 --- /dev/null +++ b/_img/negated-disjunction-decomposition-rule.svg @@ -0,0 +1,4 @@ + + + +
~(P v Q)
~(P v Q)
1
1
2
2
3
3
~P 
~P 
~Q
~Q
SM
SM
1&~vD
1&~vD
1~vD
1~vDViewer does not support full SVG 1.1 \ No newline at end of file diff --git a/_img/node-event-loop.svg b/_img/node-event-loop.svg new file mode 100644 index 0000000..a87e2d3 --- /dev/null +++ b/_img/node-event-loop.svg @@ -0,0 +1,4 @@ + + + +
index.js
index.js
call stack
call stack
Timers
Timers
I/O callbacks
I/O callbacks
Close events
Close events
I/O polling
I/O polling
setImmediate
callbacks
setImmediate...
Idle, preparation
Idle, preparation
PROCESS
PROCESS
THREAD
THREAD
TICK
TICKText is not SVG - cannot display \ No newline at end of file diff --git a/_img/nor-gate-new.png b/_img/nor-gate-new.png new file mode 100644 index 0000000..d97578f Binary files /dev/null and b/_img/nor-gate-new.png differ diff --git a/_img/not-gate-new.png b/_img/not-gate-new.png new file mode 100644 index 0000000..c2da4c5 Binary files /dev/null and b/_img/not-gate-new.png differ diff --git a/_img/one-eighth-a.png b/_img/one-eighth-a.png new file mode 100644 index 0000000..a39820d Binary files /dev/null and b/_img/one-eighth-a.png differ diff --git a/_img/or-gate-new.png b/_img/or-gate-new.png new file mode 100644 index 0000000..2d97429 Binary files /dev/null and b/_img/or-gate-new.png differ diff --git a/_img/or-transistor.svg b/_img/or-transistor.svg new file mode 100644 index 0000000..b691723 --- /dev/null +++ b/_img/or-transistor.svg @@ -0,0 +1,4 @@ + + + +
V-A
V-A
V-B
V-B
V-out
V-out
V-cc
V-cc
Trans
Trans
Trans
TransText is not SVG - cannot display \ No newline at end of file diff --git a/_img/parallel-battery-diagram.svg b/_img/parallel-battery-diagram.svg new file mode 100644 index 0000000..e8df3d3 --- /dev/null +++ b/_img/parallel-battery-diagram.svg @@ -0,0 +1,689 @@ + + + + + + + + + + + + + + + + + + + + + + + 1.5 V + + + + + + + + + + 1.5 V + 1.5 V + - + - + - + + + + + + + + 1.5 V + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + + + + + diff --git a/_img/parallel-transmission.jpg b/_img/parallel-transmission.jpg new file mode 100644 index 0000000..e7f69b1 Binary files /dev/null and b/_img/parallel-transmission.jpg differ diff --git a/_img/proof.png b/_img/proof.png new file mode 100644 index 0000000..bf3831f Binary files /dev/null and b/_img/proof.png differ diff --git a/_img/proofs-drawio-Page-5.drawio.png b/_img/proofs-drawio-Page-5.drawio.png new file mode 100644 index 0000000..8f59d18 Binary files /dev/null and b/_img/proofs-drawio-Page-5.drawio.png differ diff --git a/_img/proofs-drawio-Page-5.drawio_2.png b/_img/proofs-drawio-Page-5.drawio_2.png new file mode 100644 index 0000000..b83b8a9 Binary files /dev/null and b/_img/proofs-drawio-Page-5.drawio_2.png differ diff --git a/_img/proofs-drawio-Page-6.drawio.png b/_img/proofs-drawio-Page-6.drawio.png new file mode 100644 index 0000000..ba492af Binary files /dev/null and b/_img/proofs-drawio-Page-6.drawio.png differ diff --git a/_img/queue.svg b/_img/queue.svg new file mode 100644 index 0000000..d6720d7 --- /dev/null +++ b/_img/queue.svg @@ -0,0 +1,20 @@ + + + Artboard + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/_img/react-lifecycle.png b/_img/react-lifecycle.png new file mode 100644 index 0000000..eee57bd Binary files /dev/null and b/_img/react-lifecycle.png differ diff --git a/_img/red-encoding.svg b/_img/red-encoding.svg new file mode 100644 index 0000000..f9b5752 --- /dev/null +++ b/_img/red-encoding.svg @@ -0,0 +1,4 @@ + + + +
11111111
11111111
00000000
00000000
00000000
00000000
Red
Red
Blue
Blue
Green
Green
=
=
0xFF0000
0xFF0000Text is not SVG - cannot display \ No newline at end of file diff --git a/_img/reiteration.png b/_img/reiteration.png new file mode 100644 index 0000000..6aee327 Binary files /dev/null and b/_img/reiteration.png differ diff --git a/_img/serial-transmission.jpg b/_img/serial-transmission.jpg new file mode 100644 index 0000000..efd2c19 Binary files /dev/null and b/_img/serial-transmission.jpg differ diff --git a/_img/series-battcircuit.svg b/_img/series-battcircuit.svg new file mode 100644 index 0000000..de63e18 --- /dev/null +++ b/_img/series-battcircuit.svg @@ -0,0 +1,28 @@ + + + + + + + + + +1.5V + + + + + +1.5V + + + + + +1.5V + + + + + + + +4.5V + + \ No newline at end of file diff --git a/_img/series-battery-diagram.svg b/_img/series-battery-diagram.svg new file mode 100644 index 0000000..838766a --- /dev/null +++ b/_img/series-battery-diagram.svg @@ -0,0 +1,245 @@ + + + + + + + + + + + + + + + + + + + + + 1.5 V + 4.5 V + + + + + 1.5 V + + + + + 1.5 V + + + + + + + diff --git a/_img/server-listening.png b/_img/server-listening.png new file mode 100644 index 0000000..eb38b2d Binary files /dev/null and b/_img/server-listening.png differ diff --git a/_img/signed-conversion.png b/_img/signed-conversion.png new file mode 100644 index 0000000..8208d10 Binary files /dev/null and b/_img/signed-conversion.png differ diff --git a/_img/signed-to-unsigned.png b/_img/signed-to-unsigned.png new file mode 100644 index 0000000..ac7ba0a Binary files /dev/null and b/_img/signed-to-unsigned.png differ diff --git a/_img/sql-full-outer-join.png b/_img/sql-full-outer-join.png new file mode 100644 index 0000000..9f44f41 Binary files /dev/null and b/_img/sql-full-outer-join.png differ diff --git a/_img/sql-inner-join.png b/_img/sql-inner-join.png new file mode 100644 index 0000000..b71eb33 Binary files /dev/null and b/_img/sql-inner-join.png differ diff --git a/_img/sql-left-outer-join.png b/_img/sql-left-outer-join.png new file mode 100644 index 0000000..e27388b Binary files /dev/null and b/_img/sql-left-outer-join.png differ diff --git a/_img/sql-right-outer-join.png b/_img/sql-right-outer-join.png new file mode 100644 index 0000000..2115475 Binary files /dev/null and b/_img/sql-right-outer-join.png differ diff --git a/_img/square.svg b/_img/square.svg new file mode 100644 index 0000000..b305e27 --- /dev/null +++ b/_img/square.svg @@ -0,0 +1 @@ +0100200300400500600700051015202530RUNTIMEn \ No newline at end of file diff --git a/_img/sr_latch_diagram.png b/_img/sr_latch_diagram.png new file mode 100644 index 0000000..41c51f6 Binary files /dev/null and b/_img/sr_latch_diagram.png differ diff --git a/_img/sr_latch_logic_circuit.png b/_img/sr_latch_logic_circuit.png new file mode 100644 index 0000000..f3a2702 Binary files /dev/null and b/_img/sr_latch_logic_circuit.png differ diff --git a/_img/stack1.svg b/_img/stack1.svg new file mode 100644 index 0000000..897bf39 --- /dev/null +++ b/_img/stack1.svg @@ -0,0 +1,17 @@ + + + Artboard + + + + + + + + + + + + + + \ No newline at end of file diff --git a/_img/stack2.svg b/_img/stack2.svg new file mode 100644 index 0000000..f2d1752 --- /dev/null +++ b/_img/stack2.svg @@ -0,0 +1,17 @@ + + + Artboard + + + + + + + + + + + + + + \ No newline at end of file diff --git a/_img/step1.png b/_img/step1.png new file mode 100644 index 0000000..e9dee56 Binary files /dev/null and b/_img/step1.png differ diff --git a/_img/step2.png b/_img/step2.png new file mode 100644 index 0000000..674fc62 Binary files /dev/null and b/_img/step2.png differ diff --git a/_img/step3.png b/_img/step3.png new file mode 100644 index 0000000..7331da7 Binary files /dev/null and b/_img/step3.png differ diff --git a/_img/step4.png b/_img/step4.png new file mode 100644 index 0000000..12a57b9 Binary files /dev/null and b/_img/step4.png differ diff --git a/_img/switch-and-gate.png b/_img/switch-and-gate.png new file mode 100644 index 0000000..aae726a Binary files /dev/null and b/_img/switch-and-gate.png differ diff --git a/_img/switch-or-gate.png b/_img/switch-or-gate.png new file mode 100644 index 0000000..d621991 Binary files /dev/null and b/_img/switch-or-gate.png differ diff --git a/_img/sync-thread.svg b/_img/sync-thread.svg new file mode 100644 index 0000000..f3a6eb0 --- /dev/null +++ b/_img/sync-thread.svg @@ -0,0 +1,4 @@ + + + +
synchronous, single thread of control
synchronous, single thread of control
synchronous, 2+ threads of control
synchronous, 2+ threads of controlText is not SVG - cannot display \ No newline at end of file diff --git a/_img/systemd-global-files.png b/_img/systemd-global-files.png new file mode 100644 index 0000000..700600b Binary files /dev/null and b/_img/systemd-global-files.png differ diff --git a/_img/systemd-local-files.png b/_img/systemd-local-files.png new file mode 100644 index 0000000..b443998 Binary files /dev/null and b/_img/systemd-local-files.png differ diff --git a/_img/t-flip-flops.png b/_img/t-flip-flops.png new file mode 100644 index 0000000..208deea Binary files /dev/null and b/_img/t-flip-flops.png differ diff --git a/_img/theoremproof.png b/_img/theoremproof.png new file mode 100644 index 0000000..6c4b549 Binary files /dev/null and b/_img/theoremproof.png differ diff --git a/_img/transistor-diag.svg b/_img/transistor-diag.svg new file mode 100644 index 0000000..fb67854 --- /dev/null +++ b/_img/transistor-diag.svg @@ -0,0 +1,4 @@ + + + +
Base
Base
Collector
Collector
Emitter
Emitter
Negative-Positive-Negative (NPN) Bipolar Junction Transistor
Negative-Positive-Negative (NPN...Text is not SVG - cannot display \ No newline at end of file diff --git a/_img/transistor-off.png b/_img/transistor-off.png new file mode 100644 index 0000000..0d24182 Binary files /dev/null and b/_img/transistor-off.png differ diff --git a/_img/transistor-on.png b/_img/transistor-on.png new file mode 100644 index 0000000..4cc1441 Binary files /dev/null and b/_img/transistor-on.png differ diff --git a/_img/unsigned-to-signed.png b/_img/unsigned-to-signed.png new file mode 100644 index 0000000..0168aed Binary files /dev/null and b/_img/unsigned-to-signed.png differ diff --git a/_img/valence-shell.svg b/_img/valence-shell.svg new file mode 100644 index 0000000..f086c05 --- /dev/null +++ b/_img/valence-shell.svg @@ -0,0 +1,4 @@ + + + +
K
K
L
L
M
M
N
N
O
O
P
P
Q
Q
2
2
12
12
18
18
32
32
18
18
8
8
2
2
Valence shell
Valence shell
Designation
Designation
Max electrons
Max electronsText is not SVG - cannot display \ No newline at end of file diff --git a/_img/vertical-circuit.png b/_img/vertical-circuit.png new file mode 100644 index 0000000..940bbb5 Binary files /dev/null and b/_img/vertical-circuit.png differ diff --git a/_img/virtual-memory-diagram.jpg b/_img/virtual-memory-diagram.jpg new file mode 100644 index 0000000..b65f527 Binary files /dev/null and b/_img/virtual-memory-diagram.jpg differ diff --git a/_img/voltage-drop.png b/_img/voltage-drop.png new file mode 100644 index 0000000..c7f1bad Binary files /dev/null and b/_img/voltage-drop.png differ diff --git a/_img/xor-addition-four.png b/_img/xor-addition-four.png new file mode 100644 index 0000000..ea5ae5b Binary files /dev/null and b/_img/xor-addition-four.png differ diff --git a/_img/xor-gate-new.png b/_img/xor-gate-new.png new file mode 100644 index 0000000..9961f48 Binary files /dev/null and b/_img/xor-gate-new.png differ diff --git a/_img/xor-hdl.png b/_img/xor-hdl.png new file mode 100644 index 0000000..56dba50 Binary files /dev/null and b/_img/xor-hdl.png differ diff --git a/_img/yellow-encoding.svg b/_img/yellow-encoding.svg new file mode 100644 index 0000000..3a12161 --- /dev/null +++ b/_img/yellow-encoding.svg @@ -0,0 +1,4 @@ + + + +
11111111
11111111
11111111
11111111
00000000
00000000
Red
Red
Blue
Blue
Green
Green
=
=
0xFFFF00
0xFFFF00Text is not SVG - cannot display \ No newline at end of file diff --git a/_scripts/clean_image_directory.sh b/_scripts/clean_image_directory.sh new file mode 100755 index 0000000..5db22d0 --- /dev/null +++ b/_scripts/clean_image_directory.sh @@ -0,0 +1,10 @@ +#!/bin/bash + +# If there are images in _img/ that are not being used in the workspace, delete them +find /home/thomas/repos/computer_science/_img -type f | while read filename; do + rg "${filename##*/}" ../ --type markdown >/dev/null 2>&1 + if [ "$?" -eq 1 ]; then + echo "Deleted unused image: ${filename##*/}" + rm $filename + fi +done diff --git a/_scripts/random_revision_topic.sh b/_scripts/random_revision_topic.sh index 42b301b..079c364 100755 --- a/_scripts/random_revision_topic.sh +++ b/_scripts/random_revision_topic.sh @@ -3,7 +3,7 @@ # This script returns a random topic for me to revise # Choose source directories... -DIRS_TO_PARSE="../Computer_Architecture ../Electronics_and_Hardware ../Operating_Systems ../Programming_Languages/Shell " +DIRS_TO_PARSE="../Computer_Architecture ../Databases ../Electronics_and_Hardware ../Operating_Systems ../Programming_Languages/Shell ../Logic" # Return array of all files belonging to source dirs... for ele in $DIRS_TO_PARSE; do @@ -14,4 +14,4 @@ done RANDOM_FILE_INDEX=$(( $RANDOM % ${#FILE_MATCHES[@]} + 0 )) # Return file matching that index... -echo "Revise this topic: ${FILE_MATCHES[$RANDOM_FILE_INDEX]}" \ No newline at end of file +echo "Revise this topic: ${FILE_MATCHES[$RANDOM_FILE_INDEX]}" diff --git a/_scripts/rename_img_links.sh b/_scripts/rename_img_links.sh new file mode 100755 index 0000000..05e54ea --- /dev/null +++ b/_scripts/rename_img_links.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +# Replace all instances of `img` in Markdown image links with `_img` (to reflect new directory structure) + +find /home/thomas/repos/computer_science/ -type f -name "*.md" | while +read file; do + sed -i 's/\/img\//\/_img\//g' $file +done