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<!--replace-end-7--><!--replace-end-4--><!--replace-end-1--></head><body><div class="ui fluid container universe"><!--replace-start-2--><!--replace-start-3--><!--replace-start-6--><div class="ui text container" id="zettel-container" style="position: relative"><div class="zettel-view"><article class="ui raised attached segment zettel-content"><div class="pandoc"><h1 id="title-h1">Latches</h1><p>The <strong>combinatorial digital circuits</strong> we have looked at so far have been non-sequential. The outcome is a function of its immediate set of inputs and everything happens at once: there is no means of storing state for future use. In other words there is no <em><span class="zettel-link-container errors"><span class="zettel-link" title="Wiki-link does not refer to any existing zettel"><a>Memory</a></span></span></em>.</p><p>In contrast, the output of a <strong>sequential digital circuit</strong> depends not only on its present set of inputs but also on past inputs to the circuit. It has some knowledge of its own previous state through the existence of memory. This can be implemented via components that allow for the <strong>storage and retrieval of binary data</strong>.</p><h2 id="what-is-a-latch">What is a latch?</h2><p>A latch is a circuit component that wor</p><p>The <strong>SR Latch</strong> (for “set/reset”) has two inputs: <em>S</em> (for “set”) and <em>R</em> (for “reset”) and one output, <em>Q</em>. <em>Q</em> stands for the bit that is remembered. (There is also <em>not-Q</em> which is the opposite of whatever <em>Q</em> is currently set to.)</p><p>The SR Latch goes through the following state changes:</p><ul><li>When <em>S</em> is set to 1, output <em>Q</em> becomes 1 also</li><li>When <em>S</em> goes to 0, <em>Q</em> remains 1</li><li>When <em>R</em> is set to 1, the memory bit is cleared and <em>Q</em> becomes 0.</li><li><em>Q</em> remains at 0 even if <em>R</em> goes back to 0</li></ul><p>This is represented more clearly in the table below:</p><table class="ui table"><thead><tr><th>S</th><th>R</th><th>Q</th><th>Operation</th></tr></thead><tbody><tr><td>1</td><td>1</td><td>X</td><td>Invalid, null</td></tr></tbody></table><p>The most succinct account of a latch:</p><blockquote><p>A latch is a 1-bit memory device that has a state <em>Q</em> of either 1 or 0. The <em>S</em> input sets <em>Q</em> to 1 and the <em>R</em> input resets <em>Q</em> to 0.</p></blockquote><p><em>The representation of an SR Latch in a digital circuit diagram</em>:</p><p><img src="/static/sr_latch_diagram.png" /></p><h2 id="creating-a-latch-circuit">Creating a latch circuit</h2><p>The circuit diagram latch symbol obviously encapsulates more complex functionality that occurs at the sub-circuit level. We will demonstrate how this functionality can be achieved with two <a href="Logic_gates.md#nor-gate">NOR</a> gates.</p><p>The two gates are in a <strong>cross-coupled configuration</strong>. This basically means that the wires are crossed back on themselves such that the output of one is also an input of the other at a single stage in the sequence.</p><p>The circuit is created as follows:</p><p><img src="/static/sr_latch_logic_circuit.png" /></p><p>Interactive version:</p><iframe src="https://circuitverse.org/simulator/embed/nor-latch-0869192c-7d7b-4161-b13f-3f72c1bce8e9" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="400" width="600" allowFullScreen></iframe>
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Let's talk through the logic at each state change:
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<ul><li>When <em>S</em> is set to 1, output <em>Q</em> becomes 1 also<ul><li>N1 is receiving 1 from S and 0 from R by way of N2. This is the inversion of OR so TF equals F. Thus N1 is outputting 0.</li><li>Thus N2 is receiving 0 from N1 as its top input and 0 from R as its bottom input. It is therefore outputting 1 because with NOR, FF equals T. For this reason, <em>Q</em> is 1 because is directly connected to <em>R</em>.</li></ul></li><li>When <em>S</em> goes to 0, <em>Q</em> remains 1<ul><li>N2 is receiving 0 from N1 as the top input and 0 from R as the bottom input hence the overall input is FF which means N2 is outputting T and Q remains 1</li><li>N1 is outputting 0 because it is receiving 0 as its top input and 1 from its bottom input</li></ul></li><li>When <em>R</em> is set to 1, the memory bit is cleared and <em>Q</em> becomes 0.<ul><li>N2 is receiving 1 from R as its bottom input and 1 from the output of N1 as its top input. Therefore it is outputting TT which in NOR evaluates to F hence Q is 0</li><li>N1 is outputting 1 because it is receiving 0 from S as its top input and 0 from its bottom input coming from N2. FF equals T in NOR therefore 1 is outputting 1</li></ul></li><li><em>Q</em> remains at 0 even if <em>R</em> goes back to 0<ul><li>N2 is receiving 0 as its bottom input from R and 1 as its top input from N1. TF equals F in NOR hence the output of N2 is 0 and Q remains 0</li><li>N1 is outputting 1 because it is receiving 0 as its top input from S and 0 as its bottom input from N2. FF equals T in NOR hence N1 is 1</li></ul></li></ul></div></article><nav class="ui attached segment deemphasized backlinksPane" id="neuron-backlinks-pane"><h3 class="ui header">Backlinks</h3><ul class="backlinks"><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Logic_gates.html">Logic gates</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>An example of a composite gate would be a three-way AND. An AND with three inputs rather than the standard two that furnish the elementary AND gate. This gate would output 1 when all three gates have the value 1 and 0 otherwise. <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: The half adder and full adder"><a href="Half_adder_and_full_adder.html">Adders</a></span></span> and <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Latches"><a href="Latches.html">latche>s</a></span></span> whilst being <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Integrated circuits"><a href="Integrated_circuits.html">integrated circuits</a></span></span> are also, technically speaking, composite gates.</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Flip_flops.html">Flip-Flops</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>A flip-flop is a type of <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Latches"><a href="Latches.html">latch</a></span></span> that is connected to a <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Clock signals"><a href="Clock_signals.html">clock signal</a></span></span> and which executes in time with the clock’s pulse. (Sometimes “latch” and “flip-flop” are used interchangeably but technically a latch is flip-flop without a clock connection.)</p></div></li></ul></li><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Clock_signals.html">Clock signals</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>In the examples of digital circuits so far (i.e <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: The half adder and full adder"><a href="Half_adder_and_full_adder.html">adders</a></span></span> and <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Latches"><a href="Latches.html">latches</a></span></span>) ev
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