eolas/neuron/d0ed26d0-cdc8-4643-8c09-445408195f9b/.neuron/output/Hardware_Description_Language.html

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<!--replace-end-7--><!--replace-end-4--><!--replace-end-1--></head><body><div class="ui fluid container universe"><!--replace-start-2--><!--replace-start-3--><!--replace-start-6--><div class="ui text container" id="zettel-container" style="position: relative"><div class="zettel-view"><article class="ui raised attached segment zettel-content"><div class="pandoc"><h1 id="title-h1">Hardware Description Language</h1><p>An HDL is a declarative programming language used to describe the behaviour or structure of <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Integrated circuits"><a href="Integrated_circuits.html">digital circuits</a></span></span>. They are used to simulate the circuit and check its response.</p><p>The hardware designer specifies a chips logic by writing an HDL program which is then rigorously tested. At this stage, a <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Hardware simulation"><a href="Hardware_simulation.html">hardware simulator</a></span></span> takes the HDL program as input and creates a software representation of the chip logic. The designer can instruct the simulator to test the virtual chip on various sets of inputs. This is done to check the chips functionality but also to benchmark a variety of other parameters such as speed of computation and energy consumption.</p><p>There are many HDLs but the most popular are VHDL (“very high speed integrated-circuit description language”) and Verilog.</p><h2 id="usage-in-nand-to-tetris">Usage in <em>NAND to Tetris</em></h2><p>We wont use an actual HDL language, instead we will use a simplified toy language called HDL that is simple enough that when it is used with a simulator, we can learn the main facets of chip design. Its syntax is very similar to VHDL.</p><h2 id="demonstration-of-hdl-program">Demonstration of HDL program</h2><h3 id="boolean-function-to-enact">Boolean function to enact</h3><p>We will create an HDL program for an XOR gate that is implemented through the following arrangement of NOT, AND, and OR gates:</p><p><img src="/static/xor-hdl.png" /></p><h3 id="hdl-file-xorhdl">HDL file (<code>Xor.hdl</code>):</h3><p>Here is our HDL file:</p><pre><code class="language-none">/* Xor gate
If a!=b out=1 else out=0
*/
CHIP Xor {
IN a, b;
OUT out;
PARTS:
Not (in=a, out=nota);
Not (in=b, out=notb);
And (a=a, b=notb, out=w1);
And (a=nota, b=b, out=w2);
Or (a=w1, b=w2, out=out)
}</code></pre><h4 id="interface-chip-in-out">Interface (<code>CHIP, IN, OUT</code>)</h4><p>At the top level of the HDL program, the <code>CHIP</code> name and <code>IN</code>/<code>OUT</code> declaration is the <em>interface</em> of the chip. Here we specify our naming convention for the <code>IN</code> and <code>OUT</code> values which we will refer to in the implementation declaration in <code>PARTS</code>.</p><h4 id="implementation-parts">Implementation (<code>PARTS</code>)</h4><p>Everything under the <code>PARTS</code> section is the chip <em>implementation</em>. We can draw on composite gates in the <code>PARTS</code> declaration (e.g. <code>Not</code>, <code>And</code>, <code>Or</code>). The convention is to work from left to right when transcribing from a digital circuit diagram</p><h4 id="pins">Pins</h4><p>In an HDL program we distinguish internal pins along with the standard <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Integrated circuits"><a href="Integrated_circuits.html">input and output pins</a></span></span>. At the level of the interface, we are concerned only with input and output pins (in the example program these are <code>a</code>, <code>b</code> and <code>out</code>). It is at the level of the implementation that internal pins are encountered. In the example these are the connections between, e.g. the AND and NOT gates such as <code>And (a=a, b-notb, out=w1)</code>. This means the AND gate is receiving through its <code>a</code> pin the input <code>a</code> value and through its <code>b</code> pin the value of <code>b</code> inverted by a NOT. <code>out</code> is the value that is computed based on the input pins of <code>a</code> and <code>b</code>.</p><h3 id="test-file-xortst">Test file (<code>Xor.tst</code>)</h3><p>Along with the HDL file we also create a test file. This runs the chip against the inputs we supply, these will typically be equivalent to the (left-hand) truth-values column in a truth table which is the same as the parameters passed to a <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Boolean functions"><a href="Boolean_functions.html">Boolean function</a></span></span>, for example:</p><pre><code class="vhdl language-vhdl">load Xor.hdl
output-list a, b, out;
set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b =, eval, output;</code></pre><h3 id="output-file-xorout">Output file (<code>Xor.out</code>)</h3><p>When the test file is run against the HDL file it will generate an output file. This is effectively the result of the unit test. And will take the form of a truth table:</p><pre><code class="language-none">a | b | out
-----------
0 | 0 | 0
0 | 1 | 1
1 | 0 | 1
1 | 1 | 0</code></pre></div></article><nav class="ui attached segment deemphasized backlinksPane" id="neuron-backlinks-pane"><h3 class="ui header">Backlinks</h3><ul class="backlinks"><li><span class="zettel-link-container cf"><span class="zettel-link"><a href="Hardware_simulation.html">Hardware simulation</a></span></span><ul class="context-list" style="zoom: 85%;"><li class="item"><div class="pandoc"><p>In order to test our <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Hardware Description Language"><a href="Hardware_Description_Language.html">HDL</a></span></span> files we load them into the hardware simulator program. We will demonstrate this with the following XOR implementation:</p></div></li></ul></li></ul></nav><nav class="ui attached segment deemphasized bottomPane" id="neuron-tags-pane"><div><span class="ui basic label zettel-tag" title="Tag">nand-to-tetris</span></div></nav><nav class="ui bottom attached icon compact inverted menu blue" id="neuron-nav-bar"><!--replace-start-9--><!--replace-end-9--><a class="right item" href="impulse.html" title="Open Impulse"><i class="wave square icon"></i></a></nav></div></div><!--replace-end-6--><!--replace-end-3--><!--replace-end-2--><div class="ui center aligned container footer-version"><div class="ui tiny image"><a href="https://neuron.zettel.page"><img alt="logo" src="https://raw.githubusercontent.com/srid/neuron/master/assets/neuron.svg" title="Generated by Neuron 1.9.35.3" /></a></div></div></div></body></html>