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<!--replace-end-7--><!--replace-end-4--><!--replace-end-1--></head><body><div class="ui fluid container universe"><!--replace-start-2--><!--replace-start-3--><!--replace-start-6--><div class="ui text container" id="zettel-container" style="position: relative"><div class="zettel-view"><article class="ui raised attached segment zettel-content"><div class="pandoc"><h1 id="title-h1">Fetch, decode, execute, store</h1><p><em>Fetch, decode, execute</em> is the operating cycle of the CPU. We will run through how this works with reference to the <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: CPU architecture"><a href="CPU_architecture.html">CPU architecture</a></span></span>.</p><h2 id="fetch">Fetch</h2><h3 id="overview">Overview</h3><p>First, instructions and data are fetched from outside of the CPU chip (usually from the DRAM). In some cases, the data used by an instruction will be included with it. In other instance the instruction will reference the location where the data are held as an address.</p><h3 id="specifics">Specifics</h3><ul><li>The Program Counter register needs to keep track and sequence the different instructions that the CPU will work on. The first place it will look for an instruction is at the DRAM address <code>0000</code>, equivalent to 0 in the Program Counter register: the starting point. This is address therefore copied to the Memory Address Register for future reference.</li><li>This memory-storing event constitutes an instruction so it is copied to the Instruction Register.</li><li>As the first instruction has been fetched, the system reaches the end of the first cycle. Thus the Program counter increments by 1 to log this.</li><li>The next fetch cycle begins.</li></ul><h2 id="decode">Decode</h2><h3 id="overview-1">Overview</h3><p>Once the CPU has received the instruction, the CPU controller chip analyses it to determine which of its circuits should be used for processing.</p><h3 id="specifics-1">Specifics</h3><ul><li>Now that the instruction is fetched and stored in the RAM it needs to be decoded. It is therefore sent from the RAM to the Control Unit of the CPU. There are two parts to the instruction:<ol><li>The operation code (“op code”): the command that the computer will carry out.</li><li>The operand: an address in RAM where the data will be read and written to as part of the execution</li></ol></li><li>The Control Unit converts the operation code and operand into an instruction that is fed to the next stage in the cycle: execution. For example, for an add function, <code>add</code> would be the op code and <code>address x</code> and <code>address y</code> would be the operands, thus the instruction would be: <code>add</code> the value in <code>address x</code> to the value in <code>address y</code>.</li></ul><h2 id="execute">Execute</h2><p>Now the command will be executed. The operand is copied to the Memory Address Register and then passed to the Memory Data Register and the command is carried out by the ALU. The activities of ALU are covered in <a href="CPU_architecture.md#arithmetic-logic-unit">CPU Architecture</a> and the notes on <span class="zettel-link-container cf"><span class="zettel-link" title="Zettel: Logic gates"><a href="Logic_gates.html">Logic Gates</a></span></span>.</p><h2 id="store">Store</h2><h3 id="overview-2">Overview</h3><p>As well as telling the CPU what operation to perform, the instructions must specify where to store the result.</p><h3 id="specifics-2">Specifics</h3><ul><li>Data is stored differently depending on the instruction.</li><li>If the instruction is iterative (e.g. adding two numbers and then multiplying by another number), the instruction will tell the CPU to store the interim first value in the CPU’s <a href="CPU_architecture.md#registers">registers</a>. As these are part of the CPU, the data can be retrieved more readily. If the value is not expected to be used again immediately, it goes to the DRAM or harddisk.</li></ul></div></article><nav class="ui attached segment deemphasized backlinksPane" id="neuron-backlinks-pan
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