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								---
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								tags: [logic-gates, binary]
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								---
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											2022-06-04 14:00:04 +01:00
										 
									 
								 
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								# Logic gates
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								> [A logic gate consists in] three connections where there may or may not be
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								> some electricity. Two of those connections are places where electricity may be
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								> put into the device, and the third connection is a place where electricity may
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								> come out of the device.
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								[J.C. Scott. 2009. **But How Do It Know? The Basics of Computers for Everyone**,
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								21]
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								Logic gates are the basic building blocks of digital computing. **A logic gate
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								is an electrical circuit that has one or more than one input and only one
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								output.** The input and output points of the gate are
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								[pins](Integrated_circuits.md) The
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								input controls the output and the logic determining which types of input
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								(on/off) lead to specific outputs (on/off) is isomorphic with the
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								truth-conditions of the
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								[Boolean connectives](Truth-functional_connectives.md) specifiable in
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								terms of [truth tables](Truth-tables.md).
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								Physically, what 'travels through' the gates is electrical current and what
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								constitutes the 'gate' is a
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								[transistor](Transistors.md)
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								responding to the current. Going up a level of abstraction, the current/ charge
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								is identified with a
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								[bit](Binary_units_of_measurement.md#binary-units-of-measurement).
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								It is bits that go into the gate and bits which come out: binary information
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								that may be either 1 or 0.
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											2022-12-27 10:30:05 +00:00
										 
									 
								 
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								## Elementary and composite gates
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								We distinguish elementary from composite logic gates. An elementary gate is a
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								single gate embodying a single logical connective. It cannot be reduced any
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								lower as a logical abstraction. A composite gate is a gate made up of more than
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								one elemen>tary gate and/or other composite gates.
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								An example of a composite gate would be a three-way AND. An AND with three
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								inputs rather than the standard two that furnish the elementary AND gate. This
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								gate would output 1 when all three gates have the value 1 and 0 otherwise.
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								[Adders](Half_adder_and_full_adder.md)
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								and [latche>s](Latches.md) whilst
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								being
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								[integrated circuits](Integrated_circuits.md)
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								are also, technically speaking, composite gates.
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								## Gate interface / gate implementation
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								The gate _interface_ is an abstraction that the enables the user to think of the
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								gate simply in terms of inputs and outputs, without being conc>erned with the
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								technical details of how this is achieved. How it is achieved is the gate
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								_implementation_.
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								We can demonstrate this with the earlier example of a three-way AND. The diagram
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								below represents the gate as an interface:
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											2023-08-31 20:11:04 +01:00
										 
									 
								 
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								// Add: Interface diagram
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								Whereas this diagram presents the implementation of the gate: it shows the
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								specific combination of gates which creates the enables the behaviour
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								represented in the interface diagram.
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								// Add: Implementation diagram
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								> Importantly, a single interface may be implemented in a variety of ways. There
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								> is a one-to-many relationship at work here. From the point of view of the user
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								> interface these differences should not be detectable. This is another example
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								> of
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								> [hardware abstraction](Hardware_abstraction_and_modularity.md)
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											2022-12-06 07:54:42 +00:00
										 
									 
								 
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								## NOT gate
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								> The NOT gate inverts the value of whatever input it receives
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								### Truth conditions
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											2022-12-20 08:00:07 +00:00
										 
									 
								 
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								| $P$ | $\lnot P$ |
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								| --- | --------- |
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								| 1   | 0         |
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								| 0   | 1         |
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								### Interactive circuit
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											2023-01-18 19:52:45 +00:00
										 
									 
								 
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								<iframe src="https://circuitverse.org/simulator/embed/not-gate-aeb5f9e5-9f58-4883-b8e5-d70f6d023185?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginhe
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								### Truth conditions
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								tion) truth functional connective
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								### Symbol
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											2024-02-16 16:14:01 +00:00
										 
									 
								 
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											2022-12-06 15:10:08 +00:00
										 
									 
								 
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								### Truth conditions
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								### Truth conditions
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								| 1 | 0 | 0 | | 0 | 0 | 0 | | 0 | 0 | 0 |
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								### Interactive circuit
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											2022-12-27 10:00:06 +00:00
										 
									 
								 
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								<iframe src="https://circuitverse.org/simulator/embed/and-gate-b6937338-e83f-474b-af79-854b39c151a3?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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								## NAND gate
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								> The NAND gate inverts the truth conditions of AND.
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								### Symbol
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											2024-02-16 16:14:01 +00:00
										 
									 
								 
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											2022-12-06 15:10:08 +00:00
										 
									 
								 
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								### Truth conditions
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											2022-12-20 08:00:07 +00:00
										 
									 
								 
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								| $P$ | $Q$ | $\lnot(P \land Q)$ |
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								| --- | --- | ------------------ |
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								| 1   | 1   | 0                  |
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								| 1   | 0   | 0                  |
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								| 0   | 1   | 0                  |
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								| 0   | 0   | 1                  |
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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											2022-12-06 07:54:42 +00:00
										 
									 
								 
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								### Interactive circuit
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											2022-12-27 10:00:06 +00:00
										 
									 
								 
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								<iframe src="https://circuitverse.org/simulator/embed/nand-gate-60613ab9-9562-445e-9883-c4ea1920e206?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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											2024-02-02 15:58:13 +00:00
										 
									 
								 
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								NAND is a **universal logic gate**: equipped with just a NAND we can represent
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								every other possible logical condition. In practice with circuits, it is more
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								efficient to use specific dedicated gates (i.e OR, AND, NOT etc) for the other
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								Boolean connectives but in principle the same output can be achieved through
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								NANDs alone.
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								## OR gate
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											2024-02-02 15:58:13 +00:00
										 
									 
								 
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								> The OR gate represents the truth conditions of the
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											2024-02-17 11:57:44 +00:00
										 
									 
								 
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								> [disjunction](Truth-functional_connectives### Truth
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											2024-02-02 15:58:13 +00:00
										 
									 
								 
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								> conditions.md#disjunction) truth functional connective
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								### Symbol
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											2024-02-16 16:14:01 +00:00
										 
									 
								 
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											2022-12-06 15:10:08 +00:00
										 
									 
								 
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											2023-01-18 19:52:45 +00:00
										 
									 
								 
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								### Truth condition
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								### Truth conditions
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											2023-01-18 19:52:45 +00:00
										 
									 
								 
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								s
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											2022-12-20 08:00:07 +00:00
										 
									 
								 
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								| $P$ | $Q$ | $P \lor Q$ |
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								| --- | --- | ---------- |
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								| 1   | 1   | 1          |
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								| 1   | 0   | 1          |
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								| 0   | 1   | 1          |
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								| 0   | 0   | 0          |
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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											2023-01-18 19:52:45 +00:00
										 
									 
								 
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								### Interactive circui
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								### Truth conditions
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								t
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											2022-12-06 07:54:42 +00:00
										 
									 
								 
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											2022-12-27 10:30:05 +00:00
										 
									 
								 
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								<iframe src="https://circuitverse.org/simulator/embed/or-gate-087e4933-7963-482d-b4bf-9e130ef05706?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								## XOR gate
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								> The OR gate represents the truth conditions of the exclusive OR
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								### Symbol
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											2024-02-16 16:14:01 +00:00
										 
									 
								 
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											2022-12-06 15:10:08 +00:00
										 
									 
								 
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								### Truth conditions
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											2022-12-20 08:00:07 +00:00
										 
									 
								 
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								| $P$ | $Q$ | $\lnot(P \Leftrightarrow Q)$ |
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								| --- | --- | ---------------------------- |
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								| 1   | 1   | 0                            |
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								| 1   | 0   | 1                            |
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								| 0   | 1   | 1                            |
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								| 0   | 0   | 0                            |
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											2022-12-05 08:00:05 +00:00
										 
									 
								 
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								### Interactive circuit
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											2022-12-27 10:30:05 +00:00
										 
									 
								 
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								<iframe src="https://circuitverse.org/simulator/embed/xor-gate-a240131e-a9c3-4240-a52b-e14412fdd654?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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											2022-12-06 07:54:42 +00:00
										 
									 
								 
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								## NOR gate
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								> The NOR gate inverts the function of an OR gate
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								### Symbol
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											2024-02-16 16:14:01 +00:00
										 
									 
								 
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											2022-12-06 15:10:08 +00:00
										 
									 
								 
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											2022-12-06 07:54:42 +00:00
										 
									 
								 
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								### Truth conditions
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											2022-12-20 08:00:07 +00:00
										 
									 
								 
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								| $P$ | $Q$ | $P \lor Q$ |
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								| --- | --- | ---------- |
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								| 1   | 1   | 0          |
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								| 1   | 0   | 0          |
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								| 0   | 1   | 0          |
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								| 0   | 0   | 1          |
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											2022-12-06 07:54:42 +00:00
										 
									 
								 
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								### Interactive circuit
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											2022-12-27 10:30:05 +00:00
										 
									 
								 
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								<iframe src="https://circuitverse.org/simulator/embed/nor-gate-ac7946b4-f5d0-4c87-afd1-a2e92326d006?theme=default&display_title=false&clock_time=true&fullscreen=true&zoom_in_out=true" style="border-width:; border-style: solid; border-color:;" name="myiframe" id="projectPreview" scrolling="no" frameborder="1" marginheight="0px" marginwidth="0px" height="250" width="500" allowFullScreen></iframe>
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